United Microelectronics Corp.

Fujian Jinhua Integrated Circuit Co., Ltd.

En-Chiuan Liou

Yu-Cheng Tung

Chih-Wei Yang

Chia-Hsun Tseng

Sho-Shen Lee

Ssu-I Fu

Yi-Ting Chen

Yi-Jing Wang

Po-Chao Tsao

Chih-Sen Huang

Chia-Hung Wang

Chia-Ching Lin

Hsiao-Lin Hsu

Ching-Wen Hung

Jia-Rong Wu

Chia-Lin Lu

Chun-Chi Yu

Chia-Jui Liang

Tang-Chun Weng

Yu-Ting Hung

Che-Yi Lin

Teng-Chin Kuo

Feng-Yi Chang

Shih-Hung Tsai

Chun-Lung Chen

Kun-Yuan Liao

Chien-Hao Chen

Shin-Feng Su

I-Ming Tseng

Chao-Hung Lin

Yu-Ru Yang

Chia-Fu Hsu

Yuan-Chi Pai

Jian-Cun Ke

Rung-Yuan Lee

Yen-Pu Chen

Yu-Feng Liu

Yu-Te Chen

Meng-Lin Tsai

Mei-Chen Chen

Chien-Ying Sun

Chun-Yuan Wu

Chia-Hung Lin

Chia-Chang Hsu

Po-Wen Su

Ching-Ling Lin

Cheng-Guo Chen

Wei-Hao Huang

Chia-Chen Sun

Hon-Huei Liu

Chang-Mao Wang

Wen-Liang Huang

Kai-Lin Chuang

Tuan-Yen Yu

Jhao-Hao Lee

Wen-Chien Hsieh

Yu-Ping Wang

Li-Wei Feng

Chih-Kai Hsu

Yu-Hsiang Hung

Jyh-Shyang Jenq

Chi-Mao Hsu

Chien-Chung Huang

Chieh-Te Chen

Nien-Ting Ho

Chien-Ming Lai

An-Chi Liu

Rai-Min Huang

Shih-Fang Hong

Yi-Wen Chen

Chun-Tsen Lu

Ya-Huei Tsai

Wei-Chuan Tsai

Ming-Shing Chen

Ying-Tsung Chen

Kuei-Chun Hung

Yen-Tsai Yi

Kuan-Hung Chen

Yu-Lin Wang

Tsung-Yin Hsieh

Yu-Ting Tseng

Hung-Yi Wu

Jun-Jie Wang

Chih-Wei Wu

Chiung-Lin Hsu

Po-Tsang Chen

Chia-Jung Li

Shang-Nan Chou

Han-Lin Zeng

Jan-Fu Yang

Yu-Ying Huang

Jen-Hsiu Li

Ya-Ling Chen

Chi-Ming Huang

Yu-Chin Huang

Chan-Yuan Hu

Chih-Yu Chiang

Zheng-Feng Chen

Lu-Wei Kuo

Cheng-Hao Yang

Provided is a semiconductor structure including a first and a second conductive layers, and a first group of vias. The second conductive layer is disposed on the first conductive layer. The first group of vias is disposed between and connects the first and the second conductive layer. The first group of vias includes a first, a second, a third and a fourth vias. The first and second vias are arranged in a first column. The third and fourth vias are arranged in a second column. The first via is adjacent to the third via. The second via is adjacent to the fourth via. The extension directions of the first and second vias are orthogonal to each other, the extension directions of the third and the fourth vias are orthogonal to each other, and the extending directions of the first and the third vias are orthogonal to each other.

Semiconductor structure

A die seal ring structure includes a metal interconnect structure on a substrate, in which the metal interconnect structure includes an inter-metal dielectric (IMD) layer on the substrate and a first metal interconnection disposed in the IMD layer. Preferably, a first side of the first metal interconnection includes a comb-shape portion in a top view, a second side of the first metal interconnection includes a linear line, a third side of the first metal interconnection includes a linear line, and a fourth side of the first metal interconnection includes a linear line.

Die seal ring structure

An integrated circuit process includes the following steps. A substrate including a first area and a second area is provided. A plurality of line patterns cover the substrate of the first area, and a sacrificial line pattern covers the substrate of the second area, wherein these line patterns separate from and are orthogonal to the sacrificial line pattern. The present invention also provides an integrated circuit formed by said process. A substrate includes a first area and a second area; a plurality of line patterns cover the substrate of the first area; a slot pattern is in the substrate of the second area, wherein these line patterns are orthogonal to the slot pattern. Additionally, a plurality of line patterns cover the substrate; a sacrificial line pattern is at ends of the line patterns, wherein these line patterns separate from and are orthogonal to the sacrificial line pattern.

Integrated circuit

Provided is a manufacturing method of s semiconductor structure. The method includes: providing a substrate, wherein the substrate has a plurality of fin portions and at least one recessed portion, the at least one recessed portion is located between two adjacent fin portions of the plurality of fin portions and a bottom surface of the at least one recessed portion is lower than a surface of the substrate between the two of the plurality of fin portions; forming a doping layer on a sidewall of the plurality of fin portions, the surface of the substrate, and a sidewall and a bottom portion of the at least one recessed portion; and forming a dielectric layer on the doping layer. A top surface of the doping layer and a top surface of the dielectric layer are lower than a top surface of each of the plurality of fin portions.

Manufacturing method of semiconductor structure

A fabricating method of a semiconductor structure includes the following steps. A gate material layer is formed on a semiconductor substrate. A patterned mask layer is formed on the gate material layer. The pattern mask layer includes at least one opening exposing a part of the gate material layer. An impurity treatment is performed to the gate material layer partially covered by the pattern mask layer for forming at least one doped region in the gate material layer. An etching process is performed to remove the gate material layer including the doped region. A dummy gate may be formed by patterning the gate material layer, and the impurity treatment may be performed after the step of forming the dummy gate. The performance of the etching processes for removing the gate material layer and/or the dummy gate may be enhanced, and the gate material residue issue may be solved accordingly.

Fabricating method of semiconductor structure

Provided is a semiconductor structure including a substrate, a doping layer, and a dielectric layer. The substrate has a plurality of fin portions and at least one recessed portion, wherein the at least one recessed portion is located between two adjacent fin portions of the plurality of fin portions and a bottom surface of the at least one recessed portion is lower than a surface of the substrate between the two of the plurality of fin portions. The doping layer is disposed on a sidewall of the plurality of fin portions, the surface of the substrate, and a sidewall and a bottom portion of the at least one recessed portion. The dielectric layer is disposed on the doping layer. A top surface of the doping layer and a top surface of the dielectric layer are lower than a top surface of each of the plurality of fin portions.

A method of pattern data preparation includes the following steps. A desired pattern to be formed on a surface of a layer is inputted. A first set of beam shots are determined, and a first calculated pattern on the surface is calculated from the first set of beam shots. The first calculated pattern is rotated, so that a boundary of the desired pattern corresponding to a non-smooth boundary of the first calculated pattern is parallel to a boundary constituted by beam shots. A second set of beam shots are determined to revise the non-smooth boundary of the first calculated pattern, thereby calculating a second calculated pattern being close to the desired pattern on the surface. The present invention also provides a method of forming a pattern in a layer.

Method of pattern data preparation and method of forming pattern in layer

A manufacturing method of a semiconductor device includes the following steps. A semiconductor substrate including at least one fin structure is provided. A gate material layer is formed on the semiconductor substrate, and the fin structure is covered by the gate material layer. A trench is formed partly in the gate material layer and partly in the fin structure. An isolation structure is formed partly in the trench and partly outside the trench. At least one gate structure is formed straddling the fin structure by patterning the gate material layer after the step of forming the isolation structure. A top surface of the isolation structure is higher than a top surface of the gate structure in a vertical direction for enhancing the isolation performance of the isolation structure. A sidewall spacer is formed on sidewalls of the isolation structure, and there is no gate structure formed on the isolation structure.

Semiconductor device

The present invention provides an overlay mark, including a substrate and plural sets of first pattern block and second pattern block. A first direction and a second direction are defined on the substrate, wherein the first direction and the second direction are perpendicular to each other. In each set, the first pattern block is rotational symmetrical to the second pattern block. Each first pattern block includes a big frame and plural small frame. Each second pattern block includes a big frame and plural small frame. The width of the big frame is greater than three times of the width of the small frame. The present invention further provides a method for evaluating the stability of a semiconductor manufacturing process.

Method for evaluating stability of semiconductor manufacturing process

A semiconductor device includes a semiconductor substrate, semiconductor fins; and a first fin bump between the semiconductor fins. The first fin bump includes a first sidewall spacer. The first sidewall spacer includes a solid-state dopant source layer and an insulating buffer layer.

Semiconductor device and method for fabricating the same

The present invention provides a method for forming a dynamic random access memory (DRAM) structure, the method including: firstly, a substrate is provided, a cell region and a peripheral region are defined on the substrate, a plurality of buried word lines is then formed in the cell region of the substrate, next, a shallow trench isolation structure is formed in the peripheral region adjacent to the cell region, wherein a concave top surface is formed on the shallow trench isolation structure, afterwards, a first dummy bit line gate is formed within the shallow trench isolation structure of the peripheral area, and a second dummy bit line gate is formed in the cell region and adjacent to the first dummy bit line gate, wherein a top surface of the first dummy bit line gate is lower than a top surface of the second dummy bit line gate.

Method for forming dynamic random access memory structure

A semiconductor device and a method of forming the same, the semiconductor device includes a substrate, a plurality of fin shaped structures and an insulating layer. The substrate has a fin field-effect transistor (finFET) region, a first region, a second region and a third region. The first region, the second region and the third region have a first surface, a second surface, and a third surface, respectively, where the first surface is relatively higher than the second surface and the second surface is relatively higher than the third surface. The fin shaped structures are disposed on a surface of the fin field-effect transistor region. The insulating layer covers the first surface, the second surface and the third surface.

The present invention provides a method of fabricating a semiconductor pattern. Firstly, a substrate is provided, having an oxide layer thereon and a first material layer on the oxide layer, a first region and a second region are defined on the substrate. A first etching step is performed, to remove a portion of the first material layer in the first region, and then a plurality of first patterns are formed on the first material layer in the first region. A second composite layer is formed on the first pattern. Next, a second pattern layer is formed on the second composite layer in the first region, and a second etching step is performed, using the first pattern and the second pattern as a mask, to remove a portion of the second composite layer, a portion of the first material layer and a portion of the oxide layer.

Manufacturing method for semiconductor pattern

A method of forming a layout of a semiconductor device includes the following steps. First line patterns extend along a first direction in a first area and a second area, but the first line patterns extend along a second direction in a boundary area. Second line patterns extend along a third direction in the first area and the second area, but the second line patterns extend along a fourth direction in the boundary area, so that minimum distances between overlapping areas of the first line patterns and the second line patterns in the boundary area are larger than minimum distances between overlapping areas of the first line patterns and the second line patterns in the first area and the second area. A trimming process is performed to shade the first line patterns and the second line patterns in the boundary area and the second area.

Method of forming layout of semiconductor device

An extreme ultraviolet (EUV) mask includes: a substrate having a first region and a second region; a reflective layer on the substrate; an absorbing layer on the reflective layer; and a first recess in the absorbing layer and in part of the reflective layer on the first region. Preferably, a bottom surface of the first recess exposes a top surface of the reflective layer.

Extreme ultraviolet mask

Growing community of inventors

Tainan, Taiwan

En-Chiuan Liou