Commissariat a L'energie Atomique Et Aux Energies Alternatives

International Business Machines Corporation

Commissariat À L'énergie Atomique Et Aux Énergies Alternatives

Stmicroelectronics Gmbh

Commissariat a L'energie Atomique

Stmicroelectronics (crolles 2) Sas

Soitec

Stmicroelectronics (rousset) Sas

Emmanuel Augendre

Shay Reboh

Remi Coquand

Sylvain Maitrejean

Nicolas J Loubet

Pierre Morin

Yves Morand

Laurent Clavelier

Sylvain Barraud

Raluca Tiron

Pablo Acosta Alba

Maxime Argoud

Maud Vinet

Hubert Moriceau

Nicolas Posseme

Frank Fournel

Marek Kostrzewa

Thomas Lorne

Lamine Benaissa

Frédéric Allibert

Perrine Batude

Thomas Ernst

Aomar Halimaoui

Jean-Charles Barbe

Louis Hutin

Thierry Baron

Thomas Signamarcheix

Benoit Mathieu

Emmanuel Rolland

François Andrieu

Isabelle Bertrand

Christelle Veytizou

Jean-François Damlencourt

A semiconductor structure for radio frequency applications includes a support substrate made of silicon and comprising a mesoporous layer, a dielectric layer arranged on the mesoporous layer and a superficial layer arranged on the dielectric layer. The mesoporous layer comprises hollow pores, the internal walls of which are mainly lined with oxide. The mesoporous layer has a thickness between 3 and 40 microns and a resistivity greater than 20 kohm·cm over its entire thickness. The support substrate has a resistivity between 0.5 and 4 ohm·cm. The invention also relates to a method for producing such a semiconductor structure.

Semiconductor structure comprising a buried porous layer for RF applications

Producing a semiconductor or piezoelectric on-insulator type substrate for RF applications which is provided with a porous layer under the BOX layer and under a layer of polycrystalline semiconductor material.

RF substrate structure and method of production

A field-effect transistor including an active zone comprises a source, a channel, a drain and a control gate, which is positioned level with the channel, allowing a current to flow through the channel between the source and drain along an x-axis, the channel comprising: a first edge of separation with the source; and a second edge of separation with the drain; the channel being compressively or tensilely strained, wherein the channel includes a localized perforation or a set of localized perforations along at least the first and/or second edge of the channel so as to also create at least one shear strain in the channel. A process for fabricating the transistor is provided.

Transistor comprising a channel placed under shear strain and fabrication process

A method for manufacturing a semiconductor-on-insulator type substrate for radiofrequency applications is provided, including the steps of: directly bonding a support substrate of a single crystal material and a donor substrate including a thin layer of a semiconductor material, one or more layers of dielectric material being at a bonding interface thereof; transferring the thin layer onto the support substrate; and forming an electric charge trap region in the support substrate in contact with the one or more layers of the dielectric material present at the bonding interface, by transforming a buried zone of the support substrate into a polycrystal.

Manufacturing process of an RF-SOI trapping layer substrate resulting from a crystalline transformation of a buried layer

An electronic device is provided, including a transistor and a substrate surmounted by first through third elements, the second element being arranged between the first and the third elements and including a nano-object, a transistor channel area being formed by part of the nano-object, a first end of the nano-object being connected to the first element by a first electrode including a first part forming a first continuity of matter and a second part formed on the first part, a second end of the nano-object being connected to the third element by a second electrode including a first part forming a second continuity of matter and a second part formed on the first part, such that a lattice parameter of the second part is suited to a lattice parameter of the first part to induce a stress in the nano-object along a reference axis.

Electronic device including at least one nano-object

The invention relates to a field-effect transistor including an active zone including a source, a channel, a drain and a control gate, which is positioned level with said channel, allowing a current to flow through said channel between the source and drain along an x-axis, said channel including: a first edge of separation with said source; and a second edge of separation with said drain; said channel being compressively or tensilely strained, characterized in that said channel includes a localized perforation or a set of localized perforations along at least said first and/or second edge of said channel so as to also create at least one shear strain in said channel. The invention also relates to a process for fabricating said transistor.

The method for fabricating a field-effect transistor comprises a step of producing a sacrificial gate and first and second spacers covering first, second and third parts of successive first to fifth semiconductor nanowires of a stack. The fabricating method comprises a step of forming a channel area of the transistor, which channel area is compressively stressed and distinct from the second part of the third nanowire. The channel area is connected to a source electrode of the transistor by the first part of the second nanowire, and to a drain electrode of the transistor by the third part of the second nanowire.

Method for fabricating a field-effect transistor

A method of manufacturing a field effect transistor is provided, including supplying a substrate surmounted by first, second, and third structures, the second structure arranged between the first and the third structures and including at least one first nano-object located away from the substrate, a part of the first nano-object being configured to form a channel area of the transistor; forming electrodes of the transistor including epitaxial growth of a first material to obtain a first continuity of matter made of the first material between the second structure and the first structure, and to obtain a second continuity of matter made of the first material between the second structure and the third structure; and epitaxial growth of a second material, starting from the first material, the second material having a lattice parameter different from a lattice parameter of the first material of the first and the second continuities.

Method of manufacturing at least one field effect transistor having epitaxially grown electrodes

Techniques for optimizing junctions of a gate-all-around nanosheet device are provided. In one aspect, a method of forming a nanosheet device includes: forming an alternating series of first/second nanosheets including a first/second material as a stack on a wafer; forming a dummy gate(s) on the stack; patterning the stack into a fin stack(s) beneath the dummy gate(s); etching the fin stack(s) to selectively pull back the second nanosheets in the fin stack(s) forming pockets in the fin stack(s); filling the pockets with a strain-inducing material; burying the dummy gate(s) in a dielectric material; selectively removing the dummy gate(s) forming a gate trench(es) in the dielectric material; selectively removing either the first nanosheets or the second nanosheets from the fin stack(s); and forming a replacement gate(s) in the gate trench(es). A nanosheet device is also provided.

Optimizing junctions of gate all around structures with channel pull back

The method of manufacturing a structure comprising one or several strained semiconducting zones capable of forming one or several transistor channel regions, the method including the following steps:

Method of manufacturing a structure having one or several strained semiconducting zones that may for transistor channel regions

Manufacture of a transistor device with at least one P type transistor with channel structure strained in uniaxial compression strain starting from a silicon layer strained in biaxial tension, by amorphization recrystallization then germanium condensation.

Method for fabricating a device with a tensile-strained NMOS transistor and a uniaxial compression strained PMOS transistor

A method for making a semiconductor device, including:

Method for making a semiconductor device with a compressive stressed channel

Method for producing a semiconductor device, comprising:

Method for producing a semiconductor device with self-aligned internal spacers

A process for fabricating a gate-wrap-around field-effect transistor is provided, including providing a substrate surmounted with first and second nanowires extending in a same longitudinal direction and having a median portion covered by a first material, and first and second ends that are arranged on either side of the median portion, a periphery of which is covered by respective first and second dielectric spacers made of a second material that is different from the first material, the ends having exposed lateral faces; doping a portion of the first and second ends via the lateral faces; depositing an amorphous silicon alloy on the first and second lateral faces followed by crystallizing the alloy; and depositing a metal on either side of the nanowires to form first and second metal contacts that respectively make electrical contact with the doped portions of the first and second ends of the nanowires.

Method for fabricating a field effect transistor having a surrounding grid

Method for making a semiconductor device, comprising:

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Montbonnot, France

Emmanuel Augendre