Ultratech, Inc.

Emily M True

Ray Ellis

Albert J Crespin

Jim Woodruff

Scott Kulas

Joe Jamello

Andrew M Hawryluk

Shiyu Zhang

Raymond Ellis

Peiqian Zhao

Warren W Flack

A J Crespin

Manish Ranjan

Detlef Fuchs

Paul M Bischoff

A method of processing a reconstituted wafer that supports IC chips includes operably disposing the reconstituted wafer in a lithography tool that has a depth of focus and a focus plane and that defines exposure fields on the reconstituted wafer, wherein each exposure field includes at least one of the IC chips. The method also includes scanning the reconstituted wafer with a line scanner to measure a surface topography of the reconstituted wafer as defined by the IC chips. The method also includes, for each exposure field: i) adjusting a position and/or an orientation of the reconstituted wafer so that a photoresist layers of the IC chips within the given exposure field fall within the depth of focus; and ii) performing an exposure with the lithography tool to pattern the photoresist layers of the IC chips in the given exposure field.

Scanning methods for focus control for lithographic processing of reconstituted wafers

A Wynne-Dyson projection lens for use in an ultraviolet optical lithography system is disclosed, wherein the projection lens is configured to have reduced susceptibility to damage from ultraviolet radiation. The projection lens utilizes lens elements that are made of optical glasses that are resistant to damage from ultraviolet radiation, but that also provide sufficient degrees of freedom to correct aberrations. The glass types used for the lens elements are selected from the group of optical glasses consisting of: fused silica, S-FPL51Y, S-FSL5Y, BSM51Y and BAL15Y.

Wynne-Dyson projection lens with reduced susceptibility to UV damage

Methods and apparatuses are provided for positioning a substrate having a target that may be located on either the front-side or the backside of the substrate. The optical detector that views the target contains a signal-generating material that is substantially identical to the substrate material.

Substrate-alignment using detector of substrate material

Sub-field enhanced global alignment (SEGA) methods for aligning reconstituted wafers in a lithography process are disclosed. The SEGA methods provide the ability to accommodate chip placement errors for chips supported by a reconstituted wafer when performing a lithographic process having an overlay requirement. The SEGA methods include measuring chip locations to determine sub-fields of the reconstituted wafer over which enhanced global alignment (EGA) can be performed on the chips therein to within the overlay requirement. The SEGA methods further included individually performing EGA over the respective sub-fields. The SEGA methods take advantage of the benefits of both EGA and site-by-site alignment and are particularly applicable to wafer-level packing lithographic processes such as fan-out wafer-level packaging.

Sub-field enhanced global alignment

An apparatus for measuring the relative positions of frontside and backside alignment marks located on opposite sides of a substrate is disclosed. The apparatus includes upper and lower optical systems that allow for simultaneous imaging of frontside and backside alignment marks. The frontside and backside alignment mark images are processed to determine the relative position of the marks, as a measurement of the alignment and/or overlay performance of the tool that formed the marks on the substrate.

Dual-sided substrate measurement apparatus and methods

Growing community of inventors

San Ramon, CA, United States of America

Emily M True