Raytheon Company

Elsa K Tong

Thomas E Kazior

Kiuchul Hwang

Colin Steven Whelan

A field effect transistor device and method, such device having source and drain electrodes in ohmic contact a semiconductor. A gate electrode-field plate structure is disposed between the source and drain electrodes. The gate electrode-field plate structure comprises: a dielectric; a first metal in Schottky contact the semiconductor; and a second metal. The second metal has: a first portion disposed over and electrically connected to a portion of the first metal; and a second portion, separated from a second portion of the first metal by a portion of the dielectric and extending beyond an edge of the first metal to an edge of the second metal. The edge of the first metal is further from the drain electrode than the edge of the second metal to provide a field-plate for the field effect transistor.

Semiconductor devices having improved field plates

A method is provided for forming a self-aligned, selectively etched, double recess high electron mobility transistor. The method includes providing a semiconductor structure having a III-V substrate; a first relatively wide band gap layer, a channel layer, a second relatively wide band gap Schottky layer, an etch stop layer; a III-V third wide band gap layer on etch stop layer; and an ohmic contact layer on the third relatively wide band gap layer. A mask is provided having a gate contact aperture to expose a gate region of the ohmic contact layer. A first wet chemical etch is brought into contact with portions of the ohmic contact layer exposed by the gate contact aperture. The first wet chemical selectively removes exposed portions of the ohmic contact layer and underlying portions of the third relatively wide band gap layer. The etch stop layer inhibits the first wet chemical etch from removing portions of such etch stop layer. Next, a second wet chemical etch is brought into contact with structure etched by the first wet chemical etch. The second wet chemical etch selectively removes exposed portions of the ohmic contact layer while leaving substantially un-etched exposed portions of the third relatively wide band gap layer, the Schottky contact layer and the etch stop layer. The etch stop layer is removed. A metal layer is deposited over the mask and through gate aperture therein onto, and in Schottky contact with, the Schottky contact layer.

Method of forming a self-aligned, selectively etched, double recess high electron mobility transistor

A method for forming a gate of a field effect transistor wherein a structure is provided having: a gallium arsenide substrate; an indium gallium arsenide channel layer over the substrate; a doped aluminum gallium arsenide barrier layer over the channel layer; a gallium arsenide protective layer disposed on the donor layer; an indium gallium phosphide etch stop layer disposed over the protective layer; and a gallium arsenide source and drain contact layer disposed over the etch stop layer. A mask is provided over the surface of the structure to expose a surface portion of the contact layer. The exposed surface portion of the contact layer is subjected to a first etch and etching through the contact layer to expose an underlying surface portion of the etch stop layer. The first etch etches the contact layer at a substantially greater etch rate than the etch rate of such etch to the etch stop layer. The exposed surface portion of the etch stop layer is then subjected to a second etch and etching through the etch stop layer to expose an underlying surface portion of the protective layer. The second etch etches the etch stop layer at a substantially greater etch rate than the etch rate of such second etch to the protective layer. A gate metal is deposited over the mask and through etched portions of the etch stop layer onto, and in Schottky contact with the exposed portion of the protective layer. The method allows the formation of a gate recess by selective wet etching thereby eliminating surface damage associated with a dry etch and ungated recess. Because of the wet etching selectivity measurement of the channel current is eliminated to determine the etching end point.

Method of making pseudomorphic high electron mobility transistors

A technique for etching tub structures and vias on the backside of a wafer comprised of gallium arsenide and for providing a planar surface on said backside of the gallium arsenide wafer is described. The tubs are formed by providing a layer of resist over the backside of the gallium arsenide substrate, and this layer is patterned to provide selected areas covering regions where tub structures and vias will be provided. In the selectively exposed regions, palladium and gold are sequentially deposited. The resist pattern is then stripped, and a second resist layer pattern is deposited masking portions of the continuous conductive layer and areas where vias are to be provided. The tub structures are then provided by suitably etching the tub to undercut portions of the resist and the palladium layer. A second continuous conductive coating is then provided in the tub structure to provide a plating layer for subsequent plating of a gold film over the palladium. Preferably, the gold is plated to completely or substantially completely fill the tub. The vias are then provided on the backside of the wafer by masking the first continuous conductive coating and the tub regions and etching the unexposed regions of the substrate to provide the via holes. The via holes are then plated with a continuous conductive layer of palladium and then gold to substantially fill the via.

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Wayland, MA, United States of America

Elsa K Tong