Kla Tencor Corporation

Kla-tencor Technologies Corporation

Kla Corporation

Ellis Chang

Allen Park

Sagar A Kekare

Michael E Adel

Khurram Zafar

Amir Widmann

Peter Rose

Songnian Rong

James Norman Wiley

Carl Hess

Sterling G Watson

William Volk

Sharon McCauley

Paul Frank Marella

Richard Wallingford

Jason Z Lin

Michael John Van Riet

Chetana Bhaskar

Chen Dror

Gordon Abbott

Tal Shusterman

Ady Levy

Mark Armstrong McCord

Lisheng Gao

Martin Plihal

Brian Duffy

Masami Aoki

Kenong Wu

Kris Bhaskar

John Charles Robinson

Santosh Bhattacharyya

Mark Wagner

Grace H Chen

Junqing Huang

Zain Saidin

Chien-Huei (Adam) Chen

Yan Xiong

Craig MacNaughton

Christopher Maher

Christophe Fouquet

Jianxin Zhang

Ping Gu

Tsung-Pao Fang

SunYong Choi

YeonHo Pae

Liu-Ming Wu

Gino Marcuccilli

Chris Chih-Chien Young

Methods and systems for inspection of wafers and reticles using designer intent data are provided. One computer-implemented method includes identifying nuisance defects on a wafer based on inspection data produced by inspection of a reticle, which is used to form a pattern on the wafer prior to inspection of the wafer. Another computer-implemented method includes detecting defects on a wafer by analyzing data generated by inspection of the water in combination with data representative of a reticle, which includes designations identifying different types of portions of the reticle. An additional computer-implemented method includes determining a property of a manufacturing process used to process a wafer based on defects that alter a characteristic of a device formed on the wafer. Further computer-implemented methods include altering or simulating one or more characteristics of a design of an integrated circuit based on data generated by inspection of a wafer.

Methods and systems for inspection of wafers and reticles using designer intent data

Mixed-mode includes receiving inspection results including one or more images of a selected region of the wafer, the one or more images include one or more wafer die including a set of repeating blocks, the set of repeating blocks a set of repeating cells. In addition, mixed-mode inspection includes adjusting a pixel size of the one or more images to map each cell, block and die to an integer number of pixels. Further, mixed-mode inspection includes comparing a first wafer die to a second wafer die to identify an occurrence of one or more defects in the first or second wafer die, comparing a first block to a second block to identify an occurrence of one or more defects in the first or second blocks and comparing a first cell to a second cell to identify an occurrence of one or more defects in the first or second cells.

Method and system for mixed mode wafer inspection

Methods and systems for inspection of wafers and reticles using designer intent data are provided. One computer-implemented method includes identifying nuisance defects on a wafer based on inspection data produced by inspection of a reticle, which is used to form a pattern on the wafer prior to inspection of the wafer. Another computer-implemented method includes detecting defects on a wafer by analyzing data generated by inspection of the wafer in combination with data representative of a reticle, which includes designations identifying different types of portions of the reticle. An additional computer-implemented method includes determining a property of a manufacturing process used to process a wafer based on defects that alter a characteristic of a device formed on the wafer. Further computer-implemented methods include altering or simulating one or more characteristics of a design of an integrated circuit based on data generated by inspection of a wafer.

A semiconductor fabrication system includes a target design device and a multi-stage fabrication tool configured to fabricate one or more layers of a sample using the fabrication process. The target design device receives metrology design rules associated with a metrology tool in which the metrology design rules include criteria for one or more physical attributes of metrology targets measurable with the metrology tool. The target design device may further receive process design rules associated with a fabrication process in which the process design rules include criteria for determining process stages of the fabrication process required to fabricate structures with selected physical attributes. The target design device may further generate a target design library including a plurality of metrology targets that satisfy the metrology design rules for the metrology tool and the process design rules for the fabrication process, wherein the target design library includes specifications for fabricating the plurality of metrology targets using two or more process stages of the fabrication process based on the process design rules.

Metrology target identification, design and verification

A metrology design and verification framework is provided, which includes methods and systems for metrology structure identification in an integrated circuit design data block, design rule checking, hierarchal design of metrology target structures to minimize random errors, and metrology design rule verification of metrology target design files. In-die metrology targets are identified using various filtering methods and/or designed as hierarchical structure within dies or outside the dies. Particularly, metrology target design files are generated, which are hierarchical in structure and compatible with design rule checks. Design rule check takes into account the hierarchical and often repetitive target designs in the verification process. Layouts may be verified using design rule checks at different levels of design rules, which may be combined to remove rule violations and errors prior to actual target production.

Computer-implemented methods, computer-readable media, and systems for classifying defects detected in a memory device area on a wafer are provided.

Computer-implemented methods, computer-readable media, and systems for classifying defects detected in a memory device area on a wafer

Universal target based inspection drive metrology includes designing a plurality of universal metrology targets measurable with an inspection tool and measurable with a metrology tool, identifying a plurality of inspectable features within at least one die of a wafer using design data, disposing the plurality of universal targets within the at least one die of the wafer, each universal target being disposed at least proximate to one of the identified inspectable features, inspecting a region containing one or more of the universal targets with an inspection tool, identifying one or more anomalistic universal targets in the inspected region with an inspection tool and, responsive to the identification of one or more anomalistic universal targets in the inspected region, performing one or more metrology processes on the one or more anomalistic universal metrology targets with the metrology tool.

Method and system for universal target based inspection and metrology

Methods and systems for determining one or more parameters of a wafer inspection process are provided. One method includes acquiring metrology data for a wafer generated by a wafer metrology system. The method also includes determining one or more parameters of a wafer inspection process for the wafer or another wafer based on the metrology data.

Metrology optimized inspection

Various methods and systems for utilizing design data in combination with inspection data are provided. One computer-implemented method for binning defects detected on a wafer includes comparing portions of design data proximate positions of the defects in design data space. The method also includes determining if the design data in the portions is at least similar based on results of the comparing step. In addition, the method includes binning the defects in groups such that the portions of the design data proximate the positions of the defects in each of the groups are at least similar. The method further includes storing results of the binning step in a storage medium.

Methods and systems for utilizing design data in combination with inspection data

Inspection guided overlay metrology may include performing a pattern search in order to identify a predetermined pattern on a semiconductor wafer, generating a care area for all instances of the predetermined pattern on the semiconductor wafer, identifying defects within generated care areas by performing an inspection scan of each of the generated care areas, wherein the inspection scan includes a low-threshold or a high sensitivity inspection scan, identifying overlay sites of the predetermined pattern of the semiconductor wafer having a measured overlay error larger than a selected overlay specification utilizing a defect inspection technique, comparing location data of the identified defects of a generated care area to location data of the identified overlay sites within the generated care area in order to identify one or more locations wherein the defects are proximate to the identified overlay sites, and generating a metrology sampling plan based on the identified locations.

Inspection guided overlay metrology

A design feature in a design file including a pattern to be formed on a substrate may be selected as a metrology target, alignment target or inspection proxy. Metrology or inspection may be performed on the substrate using a printed feature on the substrate that corresponds to the design feature as a metrology target or inspection proxy.

Rule checking for metrology and inspection

Methods and systems for determining design coordinates for defects detected on a wafer are provided. One method includes aligning a design for a wafer to defect review tool images for defects detected in multiple swaths on the wafer by an inspection tool, determining a position of each of the defects in design coordinates based on results of the aligning, separately determining a defect position offset for each of the multiple swaths based on the swath in which each of the defects was detected (swath correction factor), the design coordinates for each of the defects, and a position for each of the defects determined by the inspection tool, and determining design coordinates for the other defects detected in the multiple swaths by the inspection tool by applying the appropriate swath correction factor to those defects.

Determining design coordinates for wafer defects

The present invention includes searching imagery data in order to identify one or more patterned regions on a semiconductor wafer, generating one or more virtual Fourier filter (VFF) working areas, acquiring an initial set of imagery data from the VFF working areas, defining VFF training blocks within the identified patterned regions of the VFF working areas utilizing the initial set of imagery data, wherein each VFF training block is defined to encompass a portion of the identified patterned region displaying a selected repeating pattern, calculating an initial spectrum for each VFF training block utilizing the initial set of imagery data from the VFF training blocks, and generating a VFF for each training block by identifying frequencies of the initial spectrum having maxima in the frequency domain, wherein the VFF is configured to null the magnitude of the initial spectrum at the frequencies identified to display spectral maxima.

Region based virtual fourier filter

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Saratoga, CA, United States of America

Ellis Chang