Applied Materials, Inc.

Micro Materials Inc.

University of California

Ellie Y Yieh

Srinivas D Nemani

Li-Qun Xia

Frederic Gaillard

Ludovic Godet

Dmitry Lubomirsky

Shankar Venkataraman

Qiwei Liang

Chentsau Chris Ying

Huixiong Dai

Sean S Kang

Keith Tatseun Wong

Mehul B Naik

Wai-Fan Yau

Zhong Qiang Hua

Dian Sugiarto

Tzu-Fang Huang

Yung-Cheng Lu

Farhad K Moghadam

Abhijit Basu Mallick

Christopher S Ngai

Chen-An Chen

Jun Xue

Shin-Puu Jeng

David Wingto Cheung

Chi-I Lang

Douglas A Buchberger, Jr

Muhammad M Rasheed

Mahendra Pakala

Zheng Yuan

He Ren

Arvind Sundarrajan

Young Seen Lee

Andrew C Kummel

Sriskantharajah Thirunavukarasu

Yi Zheng

Mei-Yee Shek

Anchuan Wang

Yunsang Kim

Reza Arghavani

Gary Fong

Canfeng Lai

Seon-Mee Cho

Bencherki Mebarki

Thanh Ngoc Pham

Adib M Khan

Won B Bang

Jong Mun Kim

Nitin K Ingle

Er-Xuan Ping

Yan Ye

Thorsten B Lill

Christopher Dennis Bencher

Arvind A Kumar

Visweswaren Sivaramakrishnan

Praburam Gopalraja

Ashok K Sinha

John Tolle

Hao Chen

Xinglong Chen

Kaushal Kishore Singh

Gerardo Delgadino

Raymond Hoiman Hung

Xiaoye Zhao

Thomas Jongwan Kwon

Son Van Nguyen

Michael Robert Rice

Juan Carlos Rocha-Alvarez

Michael S Barnes

Dan Maydan

Pramit Manna

Hichem M'Saad

Richard Anthony Conti

Mihaela A Balseanu

Chando Park

Peter W Lee

Girish Anant Dixit

Jeong Soo Byun

Mukund Srinivasan

Kang Sub Yim

Peter K Lee

Meihua Shen

Nicolas J Bright

Michael D Armacost

Seshadri Ramaswami

Steve G Ghanayem

Himanshu Pokharna

Douglas Buchberger

Lin Zhang

Steven J Wolf

Zihui Li

Jeffrey C Munro

Mark Naoshi Kawaguchi

Jaesoo Ahn

Tristan Yonghui Ma

M Ziaul Karim

Weimin Zeng

Shiyu Sun

Shambhu Nath Roy

Uday Mitra

A post lithography resist treatment apparatus for treating a substrate having a resist layer thereon with a fluid layer thereover includes at least one post exposure bake chamber having a substrate support having a substrate support surface thereon, and an electrode, the electrode comprising an electrode body having a substrate support facing side, the substrate support facing side having at least one recess extending inwardly thereof, and at least one projection adjacent to the recess having a substrate support facing surface thereon, wherein the substrate support is moveable to position a substrate, when supported thereon, such that an fluid layer disposed on the substrate contacts the substrate support facing surface of the projection but does not fill the recess with fluid, and the substrate facing surface of the electrode body is spaced from the substrate.

System architecture of manufacturing of semiconductor wafers

Exemplary processing methods may include forming a plasma of a silicon-containing precursor. The methods may include depositing a flowable film on a semiconductor substrate with plasma effluents of the silicon-containing precursor. The processing region may be at least partially defined between a faceplate and a substrate support on which the semiconductor substrate is seated. A bias power may be applied to the substrate support from a bias power source. The methods may include forming a plasma of a hydrogen-containing precursor within the processing region of the semiconductor processing chamber. The methods may include etching the flowable film from a sidewall of the feature within the semiconductor substrate with plasma effluents of the hydrogen-containing precursor. The methods may include densifying remaining flowable film within the feature defined within the semiconductor substrate with plasma effluents of the hydrogen-containing precursor.

Directional selective deposition

A method includes depositing a flowable film on a substrate by providing a first input flow, the first input flow including plasma effluents of a first precursor, removing a portion of the flowable film from a sidewall of a feature defined within the substrate to obtain a remaining portion of the flowable film by providing a second input flow, the second input flow including plasma effluents of a second precursor, reducing hydrogen content of the remaining portion of the flowable film to obtain a densified film by providing a third input flow, the third input flow including plasma effluents of a third precursor, and treating the densified film in accordance with a film treatment process.

Forming films with improved film quality

Described herein is a method for performing an atomic layer deposition process to form a silicon doped oxide film on a surface of the substrate. The oxide film may be a hafnium-zirconium oxide film, or a zirconium oxide film. The atomic layer deposition process may include forming the oxide layers and a silicon layer using a hydrogen peroxide as at least one of the precursors used in formation of the oxide layers.

Ultra high-k hafnium oxide and hafnium zirconium oxide films

A method and apparatus for depositing a carbon compound on a substrate includes using an inductively coupled plasma (ICP) chamber with a chamber body, a lid, an interior volume, a pumping apparatus, and a gas delivery system and a pedestal for supporting a substrate disposed within the interior volume of the ICP chamber, the pedestal has an upper portion formed from aluminum nitride with an upper surface that is configured to support and heat a substrate with embedded heating elements and a lower portion with a tube-like structure formed from aluminum nitride that is configured to support the upper portion and house electrodes for supplying power to the embedded heating elements of the upper portion, and the pedestal is configured to heat the substrate during deposition of a carbon compound film.

Methods and apparatus for carbon compound film deposition

Embodiments of the disclosure advantageously provide semiconductor devices CFET in particular and methods of manufacturing such devices having a fully strained superlattice structure with channel layers that are substantially free of defects and release layers having a reduced selective removal rate. The CFET described herein comprise a vertically stacked superlattice structure on a substrate, the vertically stacked superlattice structure comprising: a first hGAA structure on the substrate; a sacrificial layer on a top surface of the first hGAA structure, the sacrificial layer comprising silicon germanium (SiGe) having a germanium content in a range of from greater than 0% to 50% on an atomic basis; and a second hGAA structure on a top surface of the sacrificial layer. Each of the first hGAA and the second hGAA comprise alternating layers of nanosheet channel layer that comprise silicon (Si) and nanosheet release layer that comprise doped silicon germanium (SiGe).

Monolithic complementary field-effect transistors having carbon-doped release layers

A method for processing a substrate is described. The method includes forming a metal containing resist layer onto a substrate, patterning the metal containing resist layer, and performing a post exposure bake on the metal containing resist layer. The post exposure bake on the metal containing resist layer is a field guided post exposure bake operation and includes the use of an electric field to guide the ions or charged species within the metal containing resist layer. The field guided post exposure bake operation may be paired with a post development field guided bake operation.

Metal oxide resist patterning with electrical field guided post-exposure bake

A method and apparatus for performing post-exposure bake operations is described herein. The apparatus includes a plate stack and enables formation of a first high ion density plasma before the ion concentration within the first high ion density plasma is reduced using a diffuser to form a second low ion density plasma. The second low ion density plasma is an electron cloud or a dark plasma. An electric field is formed between a substrate support and the diffuser and through the second low ion density plasma during post-exposure bake of a substrate disposed on the substrate support. The second low ion density plasma electrically couples the substrate support and the diffuser during application of the electric field. The plate stack is equipped with power supplies and insulators to enable the formation or modification of a plasma within three regions of a process chamber.

Chamber and methods of treating a substrate after exposure to radiation

A method for enhancing a photoresist profile control includes applying a photoresist layer comprising a photoacid generator on an underlayer disposed on a material layer, exposing a first portion of the photoresist layer unprotected by a photomask to light radiation in a lithographic exposure process, providing a thermal energy to the photoresist layer in a post-exposure baking process, applying an electric field or a magnetic field while performing the post-exposure baking process, and drifting photoacid from the photoresist layer to a predetermined portion of the underlayer under the first portion of the photoresist layer.

Photoresist patterning process

Methods and apparatus for processing a substrate are provided herein. For example, a method includes supplying a vaporized precursor into a processing volume, supplying activated elements including ions and radicals from a remote plasma source, energizing the activated elements using RF source power at a first duty cycle to react with the vaporized precursor to deposit an SiNHfilm onto a substrate disposed in the processing volume, supplying a first process gas from the remote plasma source while providing RF bias power at a second duty cycle different from the first duty cycle to the substrate support to convert the SiNHfilm to an SiOx film, supplying a process gas mixture formed from a second process gas supplied from the remote plasma source and a third process gas supplied from the gas supply while providing RF bias power at the second duty cycle to the substrate support, and annealing the substrate.

Methods and apparatus for processing a substrate

A method for enhancing the depth of focus process window during a lithography process includes applying a photoresist layer comprising a photoacid generator on a material layer disposed on a substrate, exposing a first portion of the photoresist layer unprotected by a photomask to light radiation in a lithographic exposure process, providing a thermal energy to the photoresist layer in a post-exposure baking process, applying an electric field or a magnetic field while performing the post-exposure baking process, and dynamically changing a frequency of the electric field as generated while providing the thermal energy to the photoresist layer.

Lithography process window enhancement for photoresist patterning

Methods and apparatuses for minimizing line edge/width roughness in lines formed by photolithography are provided. In one example, a method of processing a substrate includes applying a photoresist layer comprising a photoacid generator to on a multi-layer disposed on a substrate, wherein the multi-layer comprises an underlayer formed from an organic material, inorganic material, or a mixture of organic and inorganic materials, exposing a first portion of the photoresist layer unprotected by a photomask to a radiation light in a lithographic exposure process, and applying an electric field or a magnetic field to alter movement of photoacid generated from the photoacid generator substantially in a vertical direction.

Film structure for electric field guided photoresist patterning process

The present disclosure provides methods for performing an annealing process on a metal containing layer in TFT display applications, semiconductor or memory applications. In one example, a method of forming a metal containing layer on a substrate includes supplying an oxygen containing gas mixture on a substrate in a processing chamber, the substrate comprising a metal containing layer disposed on an optically transparent substrate, maintaining the oxygen containing gas mixture in the processing chamber at a process pressure between about 2 bar and about 50 bar, and thermally annealing the metal containing layer in the presence of the oxygen containing gas mixture.

High pressure annealing process for metal containing materials

One or more embodiments described herein generally relate to patterning semiconductor film stacks. Unlike in conventional embodiments, the film stacks herein are patterned without the need of etching the magnetic tunnel junction (MTJ) stack. Instead, the film stack is etched before the MTJ stack is deposited such that the spin on carbon layer and the anti-reflective coating layer are completely removed and a trench is formed within the dielectric capping layer and the oxide layer. Thereafter, MTJ stacks are deposited on the buffer layer and on the dielectric capping layer. An oxide capping layer is deposited such that it covers the MTJ stacks. An oxide fill layer is deposited over the oxide capping layer and the film stack is polished by chemical mechanical polishing (CMP). The embodiments described herein advantageously result in no damage to the MTJ stacks since etching is not required.

Additive patterning of semiconductor film stacks

Growing community of inventors

Sunnyvale, CA, United States of America

Ellie Y Yieh