International Business Machines Corporation

Endicott Interconnect Technologies, Inc.

Elizabeth F Foster

Stephen L Tisdale

Alfred Viehbeck

Voya Rista Markovich

Jeffrey Curtis Hedrick

Frank Daniel Egitto

David John Russell

Donald Seton Farquhar

Martin J Goldberg

Harry R Bickford

Linda C Matthew

Jane M Shaw

Robert Maynard Japp

Terrence Robert O'Toole

Donald G McBride

Ali Afzali-ardakani

Raymond Thomas Galasco

Rodney T Hodgson

Shahrokh Daijavad

Steven E Molis

Ashit A Mehta

Bodil E Braren

James L Hedrick, Jr

Peter J Duke

Juan Ayala-Esquilin

David Brian Stone

Gary A Johansson

Heike Marcello

Luis Jesus Matienzo

John Steven Kresge

James Robert Wilcox

Gerald Walter Jones

David Erle Houser

Robert David Sebesta

Michael Joseph Klodowski

Jeffrey Alan Knight

Edmond Otto Fey

Francis Joseph Downes, Jr

Stephen Wesley MacQuarrie

Thomas E Kindl

Manh-Quan Tam Nguyen

Amarjit S Rai

Gregory A Kevern

Mark L Janecek

William T Wike

Anita Sargent

Konstantinos I Papathomas

Kostas I Papathomas

Natalie Barbara Feilchenfeld

Amit Kumar Sarkhel

Brian Eugene Curcio

Paul George Rickerl

Stephen Joseph Fuerniss

Ernest Bassous

James Steven Kamperman

Gobinda Das

Michael R Scheuermann

Douglas Adam Cywar

Richard William Malek

Kathleen L Covert

Donald J Mikalsen

Charles C Emmons

Charyl L Tytran

A method of making a circuitized substrate such as a laminate chip carrier in which a polymer, e.g., Teflon, is used as a dielectric layer and a promotion adhesion layer of a polymer is used to securely adhere a conductive layer thereto which is deposited by plating. The resulting product is thus able to provide extremely narrow conductive circuitry for subsequent connections, e.g., to a semiconductor chip. Electroless plating is the preferred plating method with the dielectric immersed in a solution of conductive monomers, e.g., pyrrole monomer, the solution also possibly containing a seed material such as palladium-tin.

Circuitized substrate with conductive polymer and seed material adhesion layer

The density of electronic packaging and the electrical reliability of the sub-assemblies utilizing stacked blind vias are improved by providing a blind, landless via in a first dielectric layer laminated to a conductive metal core serving as a ground plane or a power plane. A hole is provided through the dielectric layer extending to the core. A metal, such as copper, is deposited electrolytically using the metal core as the cathode, or electrolessly without seeding into the hole. The metal is deposited on the core and progressively builds in the hole to the depth required for the via. A second dielectric layer is laminated to the first, and is provided with a second layer blind via aligned with the first via. This second via may be formed by conventional plating techniques. Multiple dielectric layers with stacked blind vias can be assembled in this manner.

Electronic package with filled blinds vias

Circuitized substrate and method of making same

Method of forming filled blind vias

A method and associated structure for increasing the rate at which a chromium volume is etched when the chromium body is contacted by an acid solution such as hydrochloric acid. The etch rate is increased by a metallic or steel body in continuous electrical contact with the chromium volume, both of which are in continuous contact with the acid solution. At a temperature between about 21&#xb0; C. and about 52&#xb0; C., and a hydrochloric acid concentration (molarity) between about 1.2and about 2.4, the etch rate is at least a factor of about two greater than an etch rate that would occur in an absence of the steel body. In one embodiment, the chromium volume is a chromium layer that rests upon a conductive layer that includes a metal such as copper, wherein the acid solution is not in contact with the conductive layer. In another embodiment, the chromium volume is a chromium layer located under a conductive layer that includes a metal such as copper, wherein the steel body and the acid solution both contact the chromium layer through an opening in the conductive layer such that the opening exposes the chromium layer.

Accelerated etching of chromium

A method for fabricating circuitized substrates which reduces shorts, and does not require baking and resulting film. The method employs a photoimageable dielectric film, having a solvent content less than about 5%, and a glass transition temperature, when cured, which is greater than about 110&deg; C. A photoimageable dielectric film is provided having from about 95% to about 100% solids, and comprising: from 0% to about 30% of the solids, of a particulate rheology modifier; from about 70% to about 100% of the solids of an epoxy resin system (liquid at 20&deg; C.) comprising: from about 85% to about 99.9% epoxy resins; and from about 0.1 to 15 parts of the total resin weight, a cationic photoinitiator; from 0% to about 5% solvent; applying the photoimageable dielectric film to a circuitized substrate; and exposing the film to actinic radiation.

Photoimageable dielectric epoxy resin system film

A method of making a multi-layered interconnect structure. First and second electrically conductive members are formed on the first and second dielectric layers, respectively. The dielectric layer are formed on opposing surfaces of a thermally conductive layer. A first and second electrically conductive layer is formed within the first dielectric layer. The second electrically conductive layer includes shielded signal conductors and is positioned between the first electrically conductive layer and the thermally conductive layer. A plated through hole (PTH) formed through the interconnect structure is electrically connected to one of the first and second electrically conductive members and to one of the shielded signal conductors. A third dielectric layer, formed on the first dielectric layer and on portions of the first electrically conductive members, substantially overlies the PTH and includes a high density interconnect layer for providing an electrical path from an electronic device to the shielded signal conductors.

Method of making a multi-layered interconnect structure

A method for fabricating circuitized substrates which reduces shorts, and does not require baking and resulting film. The method employs a photoimageable dielectric film, having a solvent content less than about 5%, and a glass transition temperature, when cured, which is greater than about 110&deg; C. A photoimageable dielectric film, is provided having from about 95% to about 100% solids, and comprising: from 0% to about 30% of the solids, of a particulate rheology modifier, from about 70% to about 100% of the solids of an epoxy resin system (liquid at 20&deg; C. comprising: from about 85% to about 99.9% epoxy resins; and from about 0.1 to 15 parts of the total resin weight, a cationic photoinitiator; from 0 to about 5% solvent, applying the photoimageable dielectric film to a circuitized substrate; and exposing the film to actinic radiation.

Method of fabricating circuitized structures

Deterioration and damage to insulator materials in an interconnection structure having vertical connections due to exposure to heat during bonding of lamina is avoided by performing diffusion bonding of metal pads at plated through holes (PTH) at temperatures below the melting points of conductive material in the bond. Diffusion bonding is achieved during time periods required for processing (e.g. curing or drying) of insulating materials in the laminated structure.

Method of forming metallic z-interconnects for laminate chip packages and boards

A method and structure for forming a metalized blind via. A dielectric layer is formed on a metallic layer, followed by laser drilling a depression in the dielectric layer such that a carbon film that includes the carbon is formed on a sidewall of the depression. If the laser drilling does not expose the metallic layer, then an anisotropic plasma etching, such as a reactive ion etching (RIE), may be used to clean and expose a surface of the metallic layer. The dielectric layer includes a dielectric material having a carbon based polymeric material, such as a permanent photoresist, a polyimide, and advanced solder mask (ASM). The metallic layer includes a metallic material, such as copper, aluminum, and gold. The carbon film is in conductive contact with the metallic layer, and the carbon film is sufficiently conductive to permit electroplating a continuous layer of metal (e.g., copper) directly on the carbon film without need of an electrolessly plated layer underneath the electroplated layer. The laser drilling is accomplished using a laser radiation having a wavelength between about 180 nanometers and about 600 nanometers. The depression may have any cross-sectional shape and any spatial distribution of depths. As an example, the depression may include a blind via, a rectangular channel, or a combination thereof.

Fabrication of a metalized blind via

A method for fabricating circuitized substrates which reduces shorts, and does not require baking and resulting film. The method employs a photoimageable dielectric film, having a solvent content less than about 5%, and a glass transition temperature, when cured, which is greater than about 110&deg; C. A photoimageable dielectric film is provided having from about 95% to about 100% solids, and comprising: from 0% to about 30% of the solids, of a particulate rheology modifier; from about 70% to about 100% of the solids of an epoxy resin system (liquid at 20&deg; C.) comprising: from about 85% to about 99.9% epoxy resins; and from about 0.1 to 15 parts of the total resin weight, a cationic photoinitiator; from 0 to about 5% solvent; applying the photoimageable dielectric film to a circuitized substrate; and exposing the film to actinic radiation.

A method and structure for forming a metalized blind via. A dielectric layer is formed on a metallic layer, followed by laser drilling a depression in the dielectric layer such that a carbon film that includes the carbon is formed on a sidewall of the depression. If the laser drilling does not expose the metallic layer, then an anisotropic plasma etching, such as a reactive ion etching (RIE), may be used to clean and expose a surface of the metallic layer. The dielectric layer comprises a dielectric material having a carbon based polymeric material, such as a permanent photoresist, a polyimide, and advanced solder mask (ASM). The metallic layer includes a metallic material, such as copper, aluminum, and gold. The carbon film is in conductive contact with the metallic layer, and the carbon film is sufficiently conductive to permit electroplating a continuous layer of metal (e.g., copper) directly on the carbon film without need of an electrolessly plated layer underneath the electroplated layer. The laser drilling is accomplished using a laser radiation having a wavelength between about 180 nanometers and about 600 nanometers. The depression may have any cross-sectional shape and any spatial distribution of depths. As an example, the depression may include a blind via, then the blind via may have any cross-sectional shape, such as circular or non-circular, a rectangular channel, or a combination thereof.

An electronic package, and method of making the electronic package, is provided. The package includes a semiconductor chip and an multi-layered interconnect structure having a high density interconnect layer such as an allylated surface layer. The semiconductor chip includes a plurality of contact members on one of its surfaces that are connected to the multi-layered interconnect structure by a plurality of solder connections. The multi-layered interconnect structure is adapted for electrically interconnecting the semiconductor chip to a circuitized substrate (eg., circuit board) with another plurality of solder connections and includes a thermally conductive layer being comprised of a material having a selected thickness and coefficient of thermal expansion to substantially prevent failure of the solder connections between said first plurality of electrically conductive members and the semiconductor chip. The electronic package further includes a dielectric material having an effective modulus to assure sufficient compliancy of the multi-layered interconnect structure during operation. The allylated surface layer has the property of being able to withstand thermal stresses that arise during thermal cycling operation of the electronic package.

Electronic package with high density interconnect layer

An electrical structure, comprising a first dielectric layer, a patterned layer on the first dielectric layer, and a second dielectric layer on the patterned layer. The patterned layer includes a metal pattern on the first dielectric layer, a metallic pattern on the metal pattern, and a plugged pattern within a remaining space of the patterned layer. The plugged pattern includes a dielectric material. The second dielectric layer is adhesively bonded to a top surface of the patterned layer. The second dielectric layer includes the dielectric material.

Patterning a layered chrome-copper structure disposed on a dielectric substrate

The method for forming circuitization of the present invention provides a circuitized product which does not have a blanket seed layer and only has seed layer under the metal circuitization. Thus, short circuits between circuit lines are eliminated. It is a further advantage of the method of the present invention that it does not involve stripping portions of the seed layer. The method of the present invention requires less processing steps than conventional methods and employs positive resists which are developable by aqueous alkaline solutions. Specifically, the method of the present invention for forming circuitization in a circuit board comprising the following steps: providing a dielectric substrate; applying a positive photoresist to the dielectric substrate; then exposing the positive resist through art work corresponding to the desired circuit pattern; then developing the resist with an aqueous alkaline solution to form the circuit pattern in the resist; then applying a seeding composition to the patterned substrate of step d; exposing the remaining resist to actinic radiation; developing the remaining acidified resist with an aqueous alkaline solution to remove photoresist not coated with seed to form a seed pattern; and then electrolessly plating metal onto the seed pattern so as to form the metallized circuit pattern.

Method for pattern seeding and plating of high density printed circuit boards

Growing community of inventors

Friendsville, PA, United States of America

Elizabeth F Foster