Pdf Solutions, Incorporated

Cadence Design Systems, Inc.

Cadence Design Sysyems, Inc.

Eitan Cadouri

Roland Ruehl

Anwar Adkhamovich Irmatov

Alexander Belousov

Andrei Gratchev

Alexander Ryjov

Laurent Thenie

Min Cao

Mathew Koshy

Tianhao Zhang

Li-Ling Ma

Haifang Liao

Kenneth Mednick

Krzysztof Antoni Kozminski

Mark A Snowden

Disclosed is an improved approach for organizing, analyzing, and operating upon polygon data which significantly reduces the amount of data required for processing while keeping elements non-interfacing with each other. According to one approach, clusters of elements are extracted which are then handled separately. In some approaches, a set of polygons forms a cluster if for any two polygons from the set of polygons there exists a sequence of polygons from the set such that the distance between any sequential polygons are less than or equal to a given threshold number. Rather than analyzing each and every polygon in the design, repetitive unique patterns are analyzed once, which are then replicated for all clusters which have the same repetitive pattern.

Method and mechanism for extraction and recognition of polygons in an IC design

An improved method and mechanism for data partitioning for a DRC tool is disclosed that efficiently and effectively allows parallelization and multithreading to occur for DRC analysis of the IC design. Data partitioning is performed to allow some of the data to be processed in parallel by distributed processing units, while allowing other of the data to be processed in parallel by multiple threads. This can be accomplished by identifying different types of rules and data, and having different types of processing for the different types of rules and data. Certain types of rules/data will be processed with multi-threaded processing and other types of rules/data will be processed in parallel using distributed processing units.

Method and mechanism for performing partitioning of DRC operations

Disclosed is an improved method and system for processing the tasks performed by an EDA tool in parallel. The IC layout is divided into a plurality of layout windows and one or more of the layout windows are processed in parallel. Sampling of one or more windows may be performed to provide dynamic performance estimation.

Method and system for implementing parallel processing of electronic design automation tools

Disclosed is a method and system for processing the tasks performed by an IC layout processing tool in parallel. In some approaches, the IC layout is divided into a plurality of layout portions and one or more of the layout portions are processed in parallel, where geometric select operations are performed in which data for different layout portions may be shared between different processing entities. One approach includes the following actions: select phase one operation for performing initial select actions within layout portions; distributed regioning action for local regioning; distributed regioning action for global regioning and binary select; count select aggregation for count-based select operations; and select phase two operations for combining results of selecting of internal shapes and interface shapes.

Method and system for parallel processing of IC design layouts

Disclosed is a system and method for performing latchup checks for an IC design. In one approach, partitioning is used to create separate sections of the geometry to analyze. The data is then checked by performing graph manipulations.

Method and mechanism for performing latch-up check on an IC design

Disclosed is a method, system, and computer program product for processing design objects, such as vias, for an integrated circuit design. In one approach, pattern matching is employed to perform DRC/LVS for scattering bars and Vias. A library of via combinations can be used to insert scattering bars into design. This approach of using a library can be applied to other structures in design in addition to vias.

Method and system for using pattern matching to process an integrated circuit design

A die placement of dice to be formed on a semiconductor wafer is adjusted by obtaining a die placement and one or more locations on the wafer contacted by one or more processing structures or a substance emitted by one or more processing structures. The die placement is adjusted based on the obtained one or more locations on the wafer.

Adjusting die placement on a semiconductor wafer to increase yield

In one exemplary embodiment, yield information of semiconductor dice is mapped by obtaining yield information of a first die that was formed on a first location on a first wafer. Yield information is obtained of a second die that was formed on a second location on a second wafer. A portion of the first location corresponds to a portion of the second location such that the portion of the first location would overlap with the portion of the second location if the first location was on the second wafer. A plurality of pixel elements is defined. Each pixel element corresponds to a different location on a wafer, and at least one of the plurality of pixel elements corresponds to the portion of the first location that corresponds to the portion of the second location. An average yield is determined for the at least one of the plurality of pixel elements based on the yield information of the first die and the second die. A deviation is determined for the at least one of the plurality of pixel elements based on the average yield of the at least one of the plurality of pixel elements and the yield information of the first die and the second die.

Mapping yield information of semiconductor dice

A method and mechanism is disclosed for performing a spacing rule DRC check that does not require an excessive number of passes through the IC design. In one approach, a two-pass approach is employed to perform a spacing check. In an approach, a polygons are associated with a family of related polygons.

Method and mechanism for performing DRC processing with reduced passes through an IC design

A method of optimizing production of semiconductor devices on a wafer comprises steps of characterizing at least one effect of at least one manufacturing component on at least one optimization criterion; inputting user optimization data; and, based on the at least one effect and the user optimization data, performing optimization to determine a layout of semiconductor devices on the wafer that optimizes performance according to the user optimization data.

Optimization of die placement on wafers

Dice on a wafer are selected to be tested using a yield map. The yield map incorporates yield information of different products produced by the same fabrication process. A die placement for a product to be produced by the same process is determined based on the yield map. An expected yield for a die in the die placement is also determined based on the yield map. The expected yield for the die is then used to determine whether to test the die.

Selecting dice to test using a yield map

A die placement of dies on a wafer is selected to reduce test time of the dies by obtaining a die placement and determining placements of a tester head needed to test the dies in the die placement. A number of touchdowns needed in the determined placements of the tester head is determined, where a touchdown involves lowering the tester head to form an electrical contact between pins on the tester head and bonding pads on a die being tested. The die placement is adjusted to reduce the number of touchdowns.

Selecting die placement on a semiconductor wafer to reduce test time

Publishable yield information can be produced by obtaining an actual yield value associated with an integrated circuit (IC) or portion of an IC formed on each one of a plurality of wafers using a semiconductor wafer fabrication process. An average yield value associated with a plurality of ICs or portions of an IC formed on each one of the plurality of wafers using the semiconductor fabrication process is determined. A transformed yield value associated with the IC or portion of an IC is generated using the actual yield value and the average yield value.

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Cupertino, CA, United States of America

Eitan Cadouri