Pi R&d Co., Ltd.

Matsushita Electric Industrial Co., Ltd.

Mitsubishi Gas Chemical Company, Inc.

Eiji Nagata

Masashi Yano

Mitsuru Nozaki

Yasuo Tanaka

Morio Gaku

Akihiro Nomoto

Isao Motegi

Takabumi Omori

Norikatsu Akiyama

Hiroyuki Ishii

Yasuo Kikuchi

Fumihito Watanuki

The problem of the invention is to provide a resin composite electrolytic copper foil having further improved heat resistance and improved plate adhesion strength when plated after desmear treatment in the work process of an additive method. The solution is to form a roughened surface having a plurality of minute projections, a surface roughness (Rz) within a range of 1.0 pm to 3.0 pm and a lightness value of not more than 30 on one surface of an electrolytic copper foil (A), and form a layer of a resin composition (B) containing a block copolymerized polyimide resin (a) having a structure that imide oligomers of a first structural unit and a second structural unit are bonded alternately and repeatedly on the roughened surface.

Resin composite electrolytic copper foil, copper clad laminate and printed wiring board

A metal composite film having an excellent heat resistance and adhesion, suited for flexible printed circuit boards capable of forming fine wirings, as well as a production process thereof, is disclosed. The metal composite film comprises an insulating film; a thermoplastic polyimide layer(s) formed on at least one surface of the insulating film; and metal layers formed on the surface of each of the thermoplastic polyimide layer(s), which metal layers are formed by electroless plating and then by electrolytic plating, respectively. Since this metal composite film has an excellent heat resistance and adhesion, and maintains the excellent adhesion after forming fine wirings, it is suitably used as a high density flexible printed circuit board having fine circuits.

Process for producing metal composite film

A resin composite copper foil comprising a copper foil and a resin layer containing a block copolymer polyimide and a maleimide compound, the resin layer being formed on one surface of the copper foil, a production process thereof, a copper-clad laminate using the resin composite copper foil, a production process of a printed wiring board using the copper-clad laminate, and a printed wiring board obtained by the above process.

Resin composite copper foil, printed wiring board, and production processes thereof

A resin composite metal foil comprising a metal foil and a layer of a block copolymer polyimide resin formed on one surface of the metal foil, a metal-foil-clad laminate using the above resin composite metal foil, a printed wiring board using the above metal-foil-clad laminate, and a process for the production of a printed wiring board comprising removing an external layer metal foil of a metal-foil-clad laminate and forming a conductor layer on an external layer insulating layer by plating, wherein the metal-foil-clad laminate comprises a layer of a block copolymer polyimide resin which layer is in contact with the external layer metal foil.

Resin composite metal foil, laminate and process for the production of printed wiring board using the laminate

A method of estimating a wiring complexity degree in a semiconductor integrated circuit with a multi-layered wiring, which has a wiring structure including at least two layers or more, in laying signal wirings, includes a step of predicting a power-supply wiring space used in the semiconductor integrated circuit, a step of dividing the predicted power-supply wiring space onto respective wiring layers, and a step of estimating a complexity degree at a time of laying signal wirings, based on the predicted power-supply wiring space and a wiring specification in respective wiring layers every wiring layer.

Method of estimating wiring complexity degree in semiconductor integrated circuit

In order to avoid generation of a routing complexity of LSI and a signal rounding due to insertion of the isolation testing circuit, if a plurality of IPs are incorporated into LSI, the present invention provides an isolation testing circuits having test switching selectorstofor selecting any one of a test input signal (or a test input transit signal) and a normal input signal, and test signal transit bufferstofor relaying the test input signal (or the test input transit signal) are formed in respective IP blockstoincorporated into an LSI. Adjacent isolation testing circuits are connected mutually based on a floor plan or layout placement information such that a wiring length of a test input signaland test input transit signalsto, which are connected in a single stroke of a pen, can be reduced shortest.

Isolation testing circuit and testing circuit optimization method

An inter-block interface circuit which effectively prevents occurrences of inconveniences (for example, such that a shoot-through current flows due to unsteady potential in wiring) caused by switching off a power supply of a block, using simple circuitry, in LSI such that signals are communicated between the blocks and the power supplies of the blocks are interrupted independently. In the circuit, gate circuitsandare respectively provided in blocksandthat communicate signals with one another, and interface control circuitdynamically controls respective input levels of gate circuitsand. In other words, the circuitfixes an input level of gate circuitorin a block whose power supply is ON to 'L', and thereby compulsively fixes an output level of the gate circuit to 'L'.

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Yokohama, Japan

Eiji Nagata