Vlsi Technology, Inc.

Koninklijke Philips Corporation N.V.

Philips Electronics North America Corporation

Edward K Yeh

Calvin T Gabriel

Samit S Sengupta

Tammy D Zheng

Olivier F Laparra

A method is presented for forming a transistor gate structure. A gate oxide layer is formed. Gate material is deposited on the gate oxide layer. A layer of silicon oxynitride is deposited on the gate material. The layer of silicon oxynitride, the gate material and the gate oxide layer are etched to form a gate structure. A silicon oxynitride region remains on top of the gate structure. A wet chemical process is performed to remove the silicon oxynitride region from the top of the gate structure. After performing the wet chemical process, spacers are formed around the gate structure.

Removal of silicon oxynitride material using a wet chemical process after gate etch processing

For use with a sub-micron semiconductor process, a trench isolation process improves the etch profile of trenches among dense and isolated lines. In an example embodiment, a process forms a dielectric stack of silicon dioxide, silicon nitride and silicon oxynitride on a silicon substrate. Photolithography and etch define trench regions in the silicon substrate through the dielectric stack. Silicon oxynitride acts as a hard mask reducing differences in the sidewall slope among dense areas of the semiconductor device and the sparse areas of the semiconductor device.

Method for a consistent shallow trench etch profile

A method for preparing a semiconductor substrate for subsequent silicide formation. In one embodiment, the present invention subjects the semiconductor substrate to an ashing environment. In the present embodiment, the ashing environment is comprised of H,O vapor, and a gaseous fluorocarbon or a fluorinated hydrocarbon gas. In so doing, contaminants on the semiconductor substrate are removed. Next, the present invention subjects a mask covering a polysilicon stack to a mask-removal ashing environment. In the present embodiment, the mask-removal ashing environment is comprised of an O,plasma. In so doing, the mask covering the polysilicon stack is removed. As a result, the semiconductor substrate and the top surface of the polysilicon stack are prepared for subsequent silicide formation thereon.

Integrated process for ashing resist and treating silicon after masked spacer etch

A CF.sub.4 /H.sub.2 O.sub.2 plasma is used to remove residues remaining after an ashing step. On a substrate, a layer of photoresist is formed over an underlying layer. The layer of photoresist is developed to form a photoresist pattern. The underlying layer is etched using the photoresist pattern. The substrate, including exposed areas of the underlying layer, are subjected to a plasma comprising H.sub.2 O.sub.2 vapor and a gaseous fluorocarbon to remove residual polymers.

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San Jose, CA, United States of America

Edward K Yeh