Intel Corporation

Edward Allyn Burton

Robert J Greiner

Anant S Deval

Stephen H Gunther

Stephan Jourdan

Michael Cornaby

Douglas Robert Huard

Gerhard Schrom

Keng L Wong

Jack D Pippin

Donald S Gardner

Peter Hazucha

Linda J Rankin

Greg F Taylor

Hong-Piao Ma

Tanay Karnik

Fabrice Paillet

Jeremy J Shrall

Kaladhar Radhakrishnan

Rajesh Kumar

Douglas M Carmean

Chee How Lim

Frank Binns

John M Bauer

Trang T Nguyen

Doug Huard

Kelin J Kuhn

Shekhar Yeshwant Borkar

Gerald S Pasdast

Jonathan P Douglas

Dustin P Wood

George L Geannopoulos

Sung Tae Moon

Benson D Inkley

Richard K Hose, Jr

Arun R Ramadorai

Seng Hooi Ong

Martin M Chang

Mark T Bohr

Debendra Mallik

Mario J Paniccia

Stephen R Mooney

Bal S Sandhu

Zhiguo Qian

Nasser A Kurd

Mathew J Manusharow

Mihir K Roy

Larry E Mosley

Paul D Madland

Javed Sabir Barkatullah

Julien Sebot

Alexander Lyakhov

Tawfik M Rahal-Arabi

Hung-Piao Ma

Jerry G Jex

Jeffrey L Miller

Sunit Tyagi

William Dawson Kesling

J Keith Hodgson

Samie B Samaan

Narayanan Natarajan

Daniel Krueger

Narayanan Raghuraman

Chiu Keung Tang

Prantik K Nag

Nivruti Rai

Kumar A Anshumali

Sathya Narasimman Tiagaraj

Weimin Shi

Ravi Sankar Vunnam

Peipei Wang

Mike Cornaby

Keith-Michael W Self

Michael W Rogers

Ray Ramadorai

Anat Deval

Niraj Bindal

Murray Fitzpatrick Kelley

Shawn Michael Klauser

Mary Bloechel, Legal Representative

Anshumali Kumar

Dave Perchlik

Stacked semiconductor die architectures having one or more base dies and techniques of forming such architectures are described. The stacked semiconductor die architectures may be included in or used to form semiconductor packages. A stacked semiconductor die architecture can include: (i) one or more base dies (e.g., at least one disaggregated base die, at least one monolithic base die, etc.); and (ii) a carrier wafer having multiple stacked semiconductor dies embedded in the carrier wafer, where the carrier wafer is on the one or more base dies and where one or more interconnect structures (e.g., wires, bumps, microbumps, pillars, etc.) couple the one or more base dies to the carrier wafer and/or the stacked semiconductor dies.

Stacked semiconductor die architecture with multiple layers of disaggregation

A dual-loop low-drop (LDO) regulator having a first loop which is an analog loop that compares the voltage on the output supply node with a reference, and generates a bias or voltage control to control a strength of a final power switch. The first loop regulates the output voltage relative to a reference voltage by minimizing the error between the two voltages. A second loop (digital loop) that controls a current source which injects current on the gate of the final power switch to boost current for a load. The second loop is an auxiliary loop that boosts the current load for a set interval until the tracking bandwidth of the LDO resolves the error in the output, thereby reducing the peak-to-peak noise. The quiescent current is not increased a lot by the second loop since the second loop circuit is on for a fraction of the entire LDO operation.

Dual loop voltage regulator

An integrated circuit (IC) package, comprising a substrate that comprises a bridge die embedded within a dielectric. A first die comprising a first input/output (I/O) transmitter and a second die comprising a second I/O receiver and electrically coupled to the bridge die. A first signal trace and a first power conductor are within the bridge die. The first signal trace and the first power conductor are electrically coupled to the first I/O transmitter and the second I/O receiver. The first signal trace is to carry a digital signal and the first power conductor to provide a voltage for the second I/O receiver to read the digital signal.

Power-forwarding bridge for inter-chip data signal transfer

An apparatus and method is described that digitally coordinates dynamically adaptable clock and voltage supply to significantly reduce the energy consumed by a processor without impacting its performance or latency. A signal is generated that indicates a long latency operation. This signal is used to reduce power supply voltage and frequency of the adaptable clock. An early resume indicator is generated a few nanoseconds before normal operations are about to resume. This early resume signal is used to power up the power-downed voltage regulator, and/or can increase frequency and/or supply voltage back to normal level before normal processor operations are about to resume.

Digitally coordinated dynamically adaptable clock and voltage supply apparatus and method

Various embodiments provide a parallel arrangement of discontinuous conduction mode (DCM) voltage regulators to provide a regulated voltage to a load. The individual DCM voltage regulators may be triggered (e.g., switched to a charge state) when the regulated voltage falls below a lower threshold. Different DCM voltage regulators in the parallel arrangement may have different lower thresholds. In some embodiments, different DCM voltage regulators may include different inductance and/or transistor size (e.g., to tune the DCM voltage regulators to different current handling capabilities). Other embodiments may be described and claimed.

Voltage regulator circuit with parallel arrangement of discontinuous conduction mode voltage regulators

A computing chip can include one or more voltage regulators to decrease a standard voltage, such as twelve volts, to a relatively low operating voltage of its processing cores, typically around one volt. Because the power consumed by the cores can be substantial, such as three hundred watts or more, it is desirable to locate the voltage regulators as close as possible to the cores, to reduce the distances that relatively large currents have to travel in the chip circuitry. The voltage regulators can be embedded within the package, such as in a layered structure, in a layer that electrically connects to the cores. While the cores are typically manufactured using the smallest possible lithographic features, the voltage regulators are less demanding and can instead use relatively large lithographic features, which can be formed using relatively old technology, and can therefore be relatively inexpensive.

Semiconductor device having voltage regulators embedded in layered package

Techniques are described for fabricating integrated circuit devices that span multiple reticle fields. Integrated circuits formed within separate reticle fields are placed into electrical contact with each other by overlapping reticle fields to form an overlapping conductive interconnect. This overlapping conductive interconnect electrically connects an interconnect layer of a first reticle field with an interconnect layer of a second, laterally adjacent reticle field. The overlapping conductive interconnection extends into a common scribe zone between adjacent reticle fields.

Multiple reticle field semiconductor devices

A mesh interconnect interface includes a dielectric slice; first micro-bumps aligned along a longitudinal axis and positioned closest to a driver bank, which is to be coupled to a first mesh stop of a first chiplet; second micro-bumps similarly aligned and positioned farthest from the first driver bank; third micro-bumps similarly aligned and positioned closest to a second driver bank, which is to be coupled to a second mesh stop of a second chiplet; fourth micro-bumps similarly aligned and positioned farthest from the second driver bank, wherein the longitudinal axis is orthogonal to a gap between the chiplets. The groups of micro-bumps are disposed on the slice. A first group of wires are embedded in the slice to couple the first and second micro-bumps. A second group of wires are interleaved with the first group of wires and embedded in the slice to couple the second and third micro-bumps.

Reduction of cross-capacitance and crosstalk between three-dimensionally packed interconnect wires

Independent power control of two or more processing cores. More particularly, at least one embodiment of the invention pertains to a technique to place at least one processing core in a power state without coordinating with the power state of one or more other processing cores.

Independent power control of processing cores

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Hillsboro, OR, United States of America

Edward Allyn Burton