Intel Corporation

Tahoe Research, Ltd.

Edvin Cetegen

Omkar G Karhade

Nicholas S Haehn

Mitul Bharat Modi

Nicholas Neal

Nitin A Deshpande

Wei Ey Li

Ram S Viswanath

Sergio Antonio Chan Arguedas

Vipul V Mehta

Rahul Jain

Tarek A Ibrahim

Manish Dubey

Steve S Cho

Aastha Uppal

Thomas Heaton

Ziyin Lin

Jacob Vehonsky

Antariksh Rao Pratap Singh

Sairam Agraharam

Je-Young Chang

Yiqun Bai

Shan Zhong

Jan Krajniak

Debendra Mallik

Ravindranath Vithal Mahajan

Sanka Ganesan

Digvijay Ashokkumar Raorane

Rajendra C Dias

Nisha Ananthakrishnan

Kelly P Lofgreen

Joseph B Petrini

Mohit Bhatia

Aaron McCann

Lars D Skoglund

Yuying Wei

Sushrutha Reddy Gujjula

Kumar Abhishek Singh

Jinhe Liu

Feras Eid

Robert L Sankman

Chia-Pin Chiu

Rahul N Manepalli

Saikumar Jayaraman

Eric Jin Li

James Chris Matayabas, Jr

Gang Duan

Ashish Gupta

Chandra Mohan Jha

Christopher L Rumer

Xavier Francois Brun

Dingying David Xu

Michael L Rutigliano

Shankar Devasenathipathy

Kuang C Liu

Bassam Mohammed Ziadeh

Weihua Tang

Kyle Jordan Arrington

Taylor W Gaines

Baris Bicen

Todd R Coons

Ken P Hackenberg

Christopher Wade Ackerman

Tony Dambrauskas

George Vakanas

Arnab Choudhury

Tannaz Harirchian

Malavarayan Sankarasubramanian

Hsin-Wei Wang

Kedar Dhane

David W Song

Hsin-Yu Li

Frederick W Atadana

Sung-Won Moon

Yang Guo

Jingyi Huang

Anurag Tripathi

Mingjie Xu

Yang Jiao

Wei Li

Betsegaw Kebede Gebrehiwot

Joseph Van Nausdle

Gopi Krishnan

Mufei Yu

Shereen Elhalawaty

Vaibhav Agrawal

Soud Choudhury

Ifeanyi Okafor

Nai-Yuan Liu

Embodiments disclosed herein include electronic packages with underfill flow control features. In an embodiment, an electronic package comprises a package substrate and a plurality of interconnects on the package substrate. In an embodiment, a die is coupled to the package substrate by the plurality of interconnects and a flow control feature is adjacent on the package substrate. In an embodiment, the flow control feature is electrically isolated from circuitry of the electronic package. In an embodiment, the electronic package further comprises an underfill surrounding the plurality of interconnects and in contact with the flow control feature.

Protruding SN substrate features for epoxy flow control

Embodiments disclosed herein include electronic packages with thermal solutions. In an embodiment, an electronic package comprises a package substrate, a first die electrically coupled to the package substrate, and an integrated heat spreader (IHS) that is thermally coupled to a surface of the first die. In an embodiment, the IHS comprises a main body having an outer perimeter, and one or more legs attached to the outer perimeter of the main body, wherein the one or more legs are supported by the package substrate. In an embodiment, the electronic package further comprises a thermal block between the package substrate and the main body of the IHS, wherein the thermal block is within the outer perimeter of the main body.

Soldered metallic reservoirs for enhanced transient and steady-state thermal performance

Embodiments include semiconductor packages and a method to form such semiconductor packages. A semiconductor package includes a plurality of dies on a substrate, and an encapsulation layer over the substrate. The encapsulation layer surrounds the dies. The semiconductor package also includes a plurality of dummy silicon regions on the substrate. The dummy silicon regions surround the dies and encapsulation layer. The plurality of dummy silicon regions are positioned on two or more edges of the substrate. The dummy silicon regions have a top surface substantially coplanar to a top surface of the dies. The dummy silicon regions include materials that include silicon, metals, or highly-thermal conductive materials. The materials have a thermal conductivity of approximately 120 W/mK or greater, or is equal to or greater than the thermal conductivity of silicon. An underfill layer surrounds the substrate and the dies, where the encapsulation layer surrounds portions of the underfill layer.

Mold shelf package design and process flow for advanced package architectures

Embodiments disclosed herein include multi-die packages with open cavity bridges. In an example, an electronic apparatus includes a package substrate having alternating metallization layers and dielectric layers. The package substrate includes a first plurality of substrate pads and a second plurality of substrate pads. The package substrate also includes an open cavity between the first plurality of substrate pads and the second plurality of substrate pads, the open cavity having a bottom and sides. The electronic apparatus also includes a bridge die in the open cavity, the bridge die including a first plurality of bridge pads, a second plurality of bridge pads, and conductive traces. An adhesive layer couples the bridge die to the bottom of the open cavity. A gap is laterally between the bridge die and the sides of the open cavity, the gap surrounding the bridge die.

Open cavity bridge co-planar placement architectures and processes

No mold shelf package design and process flow for advanced package architectures

Techniques and mechanisms for facilitating heat conductivity in a packaged device with a dummy die. In an embodiment, a packaged device comprises a substrate and one or more IC die coupled to a surface thereof. A dummy die, adjacent to an IC die and coupled to a region of the substrate, comprises a polymer resin and a filler. A package mold structure of the packaged device adjoins respective sides of the IC die and the dummy die, and adjoins the surface of the substrate. In another embodiment, a first CTE of the dummy die is less than a second CTE of the package mold structure, and a first thermal conductivity of the dummy die is greater than a second thermal conductivity of the package mold structure.

Dummy die structures of a packaged integrated circuit device

An integrated circuit assembly may be formed comprising an electronic substrate, a first and second integrated circuit device each having a first surface, a second surface, at least one side extending between the first and second surface, and an edge defined at an intersection of the second surface and the at least one side of each respective integrated circuit device, wherein the first surface of each integrated circuit device is electrically attached to the electronic substrate, an underfill material between the first surface of each integrated circuit device and the electronic substrate, and between the sides of the first and second integrated circuit devices, and at least one barrier structure adjacent at least one of the edge of first integrated circuit device and the edge of the second integrated circuit device, wherein the underfill material abuts the at least one barrier structure.

Barrier structures for underfill containment

Embodiments herein relate to systems, apparatuses, or processes directed to a substrate that includes a first region to be coupled with a die, and a second region separate and distinct from the first region that has a lower thermal conductivity than the first region, where the second region is to thermally insulate the first region when the die is coupled to the first region. The thermal insulation of the second region may be used during a TCB process to increase the quality of each of the interconnects of the die by promoting a higher temperature at the connection points to facilitate full melting of solder.

Substrate with thermal insulation

Disclosed herein are structures and techniques for underfill flow management in electronic assemblies. For example, in some embodiments, an electronic assembly may include a first component, a second component, an underfill on the first component and at least partially between the first component and the second component, and a material at a surface of the first component, wherein the material is outside a footprint of the second component, and the underfill contacts the material with a contact angle greater than 50 degrees.

Underfill flow management in electronic assemblies

Disclosed herein are microelectronic structures including bridges, as well as related assemblies and methods. In some embodiments, a microelectronic structure may include a substrate and a bridge.

Microelectronic structures including bridges

Underfill material flow control for reduced die-to-die spacing in semiconductor packages and the resulting semiconductor packages are described. In an example, a semiconductor apparatus includes first and second semiconductor dies, each having a surface with an integrated circuit thereon coupled to contact pads of an uppermost metallization layer of a common semiconductor package substrate by a plurality of conductive contacts, the first and second semiconductor dies separated by a spacing. A barrier structure is disposed between the first semiconductor die and the common semiconductor package substrate and at least partially underneath the first semiconductor die. An underfill material layer is in contact with the second semiconductor die and with the barrier structure, but not in contact with the first semiconductor die.

Underfill material flow control for reduced die-to-die spacing in semiconductor packages

Embodiments include semiconductor packages. A semiconductor package includes dies on a package substrate, an integrated heat spreader (IHS) with a lid and sidewalls over the dies and package substrate, and a heatsink and a thermal interface material respectively on the IHS. The semiconductor package includes a vapor chamber defined by a surface of the package substrate and surfaces of the lid and sidewalls, and a wick layer in the vapor chamber. The wick layer is on the dies, package substrate, and IHS, where the vapor chamber has a vapor space defined by surfaces of the wick layer and lid of the IHS. The sidewalls are coupled to the package substrate with a sealant that hermetically seals the vapor chamber with the surfaces of the package substrate and the sidewalls and lid. The wick layer has a uniform or non-uniform thickness, and has porous materials including metals, powders, or graphite.

Full package vapor chamber with IHS

Multichip semiconductor package including a bridge die disposed in a cavity having non-planar interconnects

Growing community of inventors

Chandler, AZ, United States of America

Edvin Cetegen