Freescale Semiconductor,inc.

Nxp USA, Inc.

Edouard De Frésart

Ganming Qin

Robert W Baird

Moaniss Zitouni

Pon Sung Ku

Ljubo Radic

Peilin Wang

Michael F Petras

Dragan Zupac

Xin Lin

Patrice M Parris

Richard J De Souza

Evgueniy Nikolov Stefanov

Jingjing Chen

Jennifer H Morrison

Hongwei Zhou

Embodiments of semiconductor devices and methods of their formation include providing a semiconductor substrate having a top surface, a bottom surface, an active region, and an edge region, and forming a gate structure in a first trench in the active region of the semiconductor substrate. A termination structure is formed in a second trench in the edge region of the semiconductor substrate. The termination structure has an active region facing side and a device perimeter facing side. The method further includes forming first and second source regions of the first conductivity type are formed in the semiconductor substrate adjacent both sides of the gate structure. A third source region is formed in the semiconductor substrate adjacent the active region facing side of the termination structure. The semiconductor device may be a trench metal oxide semiconductor device, for example.

Methods of manufacturing trench semiconductor devices with edge termination structures

A semiconductor device includes a semiconductor layer disposed at a substrate and a plurality of active cells disposed at the semiconductor layer. Each active cell includes a trench extending into the semiconductor layer and a body region disposed in the semiconductor layer adjacent to a sidewall of the trench and at a first depth below the surface of the semiconductor layer. The semiconductor device further includes a termination cell disposed at the semiconductor layer adjacent to an edge of the plurality of active cells. The termination cell includes a trench extending into the semiconductor layer, and further includes a body region disposed in the semiconductor layer adjacent to a sidewall of the trench of the termination cell and at a second depth less than the first depth. The body regions of the active cells and of the termination cell have a conductivity type different than that of the semiconductor layer.

Edge termination for trench gate FET

A device includes a semiconductor substrate having a surface, a trench in the semiconductor substrate extending vertically from the surface, a body region laterally adjacent the trench, spaced from the surface, having a first conductivity type, and in which a channel is formed during operation, a drift region between the body region and the surface, and having a second conductivity type, a gate structure disposed in the trench alongside the body region, recessed from the surface, and configured to receive a control voltage is applied to control formation of the channel, and a gate dielectric layer disposed along a sidewall of the trench between the gate structure and the body region. The gate structure and the gate dielectric layer have a substantial vertical overlap with the drift region such that electric field magnitudes in the drift region are reduced through application of the control voltage.

Bidirectional trench FET with gate-based resurf

A semiconductor device includes a substrate and a semiconductor layer having a first conductivity type. The semiconductor device further includes first and second trenches extending into the semiconductor layer from a surface of the semiconductor layer, each of the first and second trenches including a corresponding gate electrode. The semiconductor device further includes a body region having a second conductivity type different than the first conductivity type and a source contact region having the first conductivity type. The body region is disposed in the semiconductor layer below the surface of the semiconductor layer and between a sidewall of the first trench and an adjacent sidewall of a second trench. The source contact region is disposed in the semiconductor layer between the body region and the surface of the semiconductor layer and extending between the sidewall of the first trench and the corresponding sidewall of the second trench.

Trench gate FET with self-aligned source contact

Power device termination structures and methods are disclosed herein. The structures include a trenched-gate semiconductor device. The trenched-gate semiconductor device includes a semiconducting material and an array of trenched-gate power transistors. The array defines an inner region including a plurality of inner transistors and an outer region including a plurality of outer transistors. The inner transistors include a plurality of inner trenches that has an average inner region spacing. The outer transistors include a plurality of outer trenches that has an average termination region spacing. The average termination region spacing is greater than the average inner region spacing or is selected such that a breakdown voltage of the plurality of outer transistors is greater than a breakdown voltage of the plurality of inner transistors.

Power device termination structures and methods

A high voltage vertical field effect transistor device () is fabricated in a substrate () using angled implantations () into trench sidewalls formed above recessed gate poly layers () to form self-aligned N+ regions () adjacent to the trenches and along an upper region of an elevated substrate. With a trench fill insulator layer () formed over the recessed gate poly layers (), self-aligned P+ body contact regions () are implanted into the elevated substrate without counter-doping the self-aligned N+ regions (), and a subsequent recess etch removes the elevated substrate, leaving self-aligned N+ source regions (-) and P+ body contact regions (-).

Trench FET with source recess etch

Embodiments of a semiconductor device include a semiconductor substrate having a first surface and a second surface opposed to the first surface, a trench formed in the semiconductor substrate and extending from the first surface partially through the semiconductor substrate, a gate electrode material deposited in the trench, and a void cavity in the semiconductor substrate between the gate electrode material and the second surface. A portion of the semiconductor substrate is located between the void cavity and the second surface.

Semiconductor devices having reduced gate-drain capacitance

Field effect devices and ICs with very low gate-drain capacitance Cgd are provided by forming a substantially empty void between the gate and the drain regions. For vertical FETS a cavity is etched in the semiconductor (SC) and provided with a gate dielectric liner. A poly-SC gate deposited in the cavity has a central fissure (empty pipe) extending through to the underlying SC. This fissure is used to etch the void in the SC beneath the poly-gate. The fissure is then closed by a dielectric plug formed by deposition or oxidation without significantly filling the etched void. Conventional process steps are used to provide the source and body regions around the cavity containing the gate, and to provide a drift space and drain region below the body region. The etched void between the gate and drain provides lower Cgd and Ron*Qg than can be achieved using low k dielectrics.

Semiconductor devices with enclosed void cavities

Electronic elements with very low resistance back-side coupling are provided by forming one or more narrow trenches or pipes, preferably dielectric lined, in front sides of substrates, filling the trenches or pipes with a conductor having a coefficient of expansion not too different from that of the substrate but of higher conductivity, forming an epitaxial SC layer over the front side of the substrate in Ohmic contact with the conductor the trenches or pipes, forming various semiconductor (SC) devices in the epi-layer, back grinding the substrate to expose bottoms of the conductor filled trenches or pipes, and providing a back-side conductor contacting the conductor in the trenches or pipes. For silicon SCs, tungsten is a suitable conductor for filling the trenches or pipes to minimize substrate stress. Series ON-resistance of the elements due to the substrate resistance is substantially reduced.

Semiconductor devices with low resistance back-side coupling

A TMOS device () is formed using a semiconductor layer () of a first type. First and second regions () of the second type are formed in the semiconductor layer and are spaced apart. A third region () is formed in the semiconductor layer by implanting. The third region is between and contacts the first and second doped regions, is of the second conductivity type, and is less heavily doped than the first and second doped regions. A gate stack () is formed over a portion of the first doped region, a portion of the second doped region, and the third doped region. By implanting after forming the gate stack, fourth and fifth regions () of the first type are formed in interior portions of the first and second doped regions, respectively. The third region being of the same conductivity type as the first and second regions reduces Miller capacitance.

High voltage TMOS semiconductor device with low gate charge structure and method of making

Electronic elements () with very low resistance back-side coupling are provided by forming one or more narrow trenches or pipes (), preferably dielectric lined, in front sides () of substrates ('), filling the trenches or pipes with a conductor () having a coefficient of expansion not too different from that of the substrate (&#x2032;) but of higher conductivity, forming an epitaxial SC layer () over the front side () of the substrate (&#x2032;) in Ohmic contact with the conductor () in the trenches or pipes (), forming various semiconductor (SC) devices () in the epi-layer (), back grinding the substrate (&#x2032;) to expose bottoms () of the conductor filled trenches or pipes (), and providing a back-side conductor () contacting the conductor () in the trenches or pipes (). For silicon SCs, tungsten is a suitable conductor () for filling the trenches or pipes () to minimize substrate stress. Series ON-resistance of the elements () due to the substrate resistance is substantially reduced.

Methods for forming semiconductor devices with low resistance back-side coupling

Embodiments of a method for fabricating a semiconductor device having a reduced gate-drain capacitance are provided. In one embodiment, the method includes the steps of etching a trench in a semiconductor substrate utilizing an etch mask, widening the trench to define overhanging regions of the etch mask extending partially over the trench, and depositing a gate electrode material into the trench and onto the overhanging regions. The gate electrode material merges between the overhanging regions prior to the filling of the trench to create an empty fissure within the trench. A portion of the semiconductor substrate is removed through the empty fissure to form a void cavity proximate the trench.

Methods for fabricating semiconductor devices having reduced gate-drain capacitance

Semiconductor structures (---) and methods (-) are provided for a semiconductor devices employing strained () and relaxed () semiconductors, The method comprises, forming () on a substrate () first (-) and second (-) regions of a first semiconductor material () of a first conductivity type and a first lattice constant spaced apart by a gap or trench (), filling () the trench or gap () with a second semiconductor material () of a second, conductivity type and a second different lattice constant so that the second semiconductor material () is strained with respect to the first semiconductor material () and forming () device regions (, S, G, D) communicating with the first () and second () semiconductor materials and adapted to provide device current () through at least part of the strained second semiconductor material () in the trench (). In a preferred embodiment, the relaxed semiconductor material isSi:Ge and the strained semiconductor material is substantially Si.

Strained semiconductor power device and method

Semiconductor structures and methods are provided for a semiconductor device () employing a superjunction structure () and overlying trench () with embedded control gate (). The method comprises, forming (--) interleaved first (----, etc.) and second (---, etc.) spaced-apart regions of first () and second () semiconductor materials of different conductivity type and different mobilities so that, in a first embodiment, the second semiconductor material () has a higher mobility for the same carrier type than the first semiconductor material (), and providing (-) an overlying third semiconductor material () in which a trench () is formed with sidewalls () having thereon a fourth semiconductor material () that has a higher mobility than the third material (), adapted to carry current () between source regions (), through the fourth () semiconductor material in the trench () and the second semiconductor material () in the device drift space () to the drain (). In a further embodiment, the first () and third () semiconductor materials are relaxed materials and the second () and fourth () semiconductor materials are strained semiconductor materials.

Superjunction trench device and method

Means and methods are provided for trench TMOS devices (-), comprising, providing a first semiconductor () of a first composition having an upper surface (), with a body portion () proximate the upper surface (), a drift portion () spaced apart from the upper surface () and a trench () having sidewalls () extending from the upper surface () into the drift portion (). A second semiconductor () adapted to provide a higher mobility layer is applied on the trench sidewalls () where parts () of the body portion () are exposed. A dielectric () covers the higher mobility layer () and separates it from a control gate () in the trench (). Source regions () formed in the body portion () proximate the upper surface () communicate with the higher mobility layer (). When biased, source-drain current () flows from the source regions () through gate induced channels () in the higher mobility layer () and into the drift portion () where it is extracted by a drain () or other connection coupled to the drift portion ().

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Tempe, AZ, United States of America

Edouard De Frésart