Freescale Semiconductor,inc.

Motorola Corporation

Nxp Usa, Inc.

Semiconductor Components Industries, LLC

Edouard D De Fresart

Ganming Qin

Pon Sung Ku

Peilin Wang

Moaniss Zitouni

Jingjing Chen

John W Steele

Evgueniy Nikolov Stefanov

Michael F Petras

Dragan Zupac

Wenyi Li

Pak M Tam

Hak-Yam Tsoi

N David Theodore

Patrice M Parris

Richard J De Souza

Hang M Liaw

Philippe Dupuy

Hubert Grandry

Evgueniy Stafanov

A recess is formed at a semiconductor layer of a device to define a plurality of mesas. An active trench portion of the recess residing between adjacent mesas. A termination portion of the trench residing between the end of each mesa and a perimeter of the recess. The transverse spacing between the mesas and the lateral spacing between the mesas and an outer perimeter of a recess forming the mesas are substantially the same. A shield structure within the trench extends from the region between the mesas to the region between the ends of the mesas and the outer perimeter of the recess forming the mesas. A contact resides between a shield electrode terminal and the shield portion residing in the trench.

Trench MOSFET shield poly contact

A semiconductor device comprises a first contact layer, a first drift layer adjacent the first contact layer, a buried body layer adjacent the first drift layer and a second contact layer. A first vertical trench and a second vertical trench are provided, the first and second vertical trenches being spaced with respect to each other and extending from the second contact layer to substantially beyond the buried body layer. A second drift layer is also provided and sandwiched between the buried body layer and the second contact layer.

Semiconductor device and method of manufacture therefor

A bi-directional trench field effect power transistor. A layer stack extends over the top surface of the substrate, in which vertical trenches are present. An electrical path can be selectively enabled or disabled to allow current to flow in opposite directions through a body located laterally between the first and second vertical trenches. A shallow trench, more shallow than the first vertical trench and the second vertical trench is located between the first vertical trench and the second vertical trench and extend in the vertical direction from the top layer of the stack into the body, beyond an upper boundary of the body. The body is provided with a dopant, the concentration of the dopant is at least one order of magnitude higher in a region adjacent to the shallow trench than near the first vertical trench and the second vertical trench.

Bidirectional power transistor with shallow body trench

An integrated circuit comprises a transistor body control circuit for controlling a body of a bidirectional power transistor. The transistor body control circuit comprises switches connected between a body terminal and a first current terminal, with a control terminal for controlling the current flowing through the switch. The control terminal of the switch is connected to alternating current, AC capacitive voltage divider. The AC capacitive voltage dividers are connected to the control terminals and arranged to control the switches to switch the voltage of the body terminal as a function of the voltage between the first current terminal and the second current terminal. The integrated circuit further comprises a bi-directional power transistor connected to the transistor body control circuit.

Transistor body control circuit and an integrated circuit

Embodiments of semiconductor devices and methods of their formation include providing a semiconductor substrate having a top surface, a bottom surface, an active region, and an edge region, and forming a gate structure in a first trench in the active region of the semiconductor substrate. A termination structure is formed in a second trench in the edge region of the semiconductor substrate. The termination structure has an active region facing side and a device perimeter facing side. The method further includes forming first and second source regions of the first conductivity type are formed in the semiconductor substrate adjacent both sides of the gate structure. A third source region is formed in the semiconductor substrate adjacent the active region facing side of the termination structure. The semiconductor device may be a trench metal oxide semiconductor device, for example.

Methods of manufacturing trench semiconductor devices with edge termination structures

A power MOSFET has a main-FET (MFET) and an embedded current sensing-FET (SFET). MFET gate runners are coupled to SFET gate runners by isolation gate runners (IGRs) in a buffer space between the MFET and the SFET. In one embodiment, n IGRs (i=1 to n) couple n+1 gates of a first portion of the MFET () to n gates of the SFET. The IGRs have zigzagged central portions where each SFET gate runner is coupled via the IGRs to two MFET gate runners. The zigzagged central portions provide barriers that block parasitic leakage paths, between sources of the SFET and sources of the MFET, for all IGRs except the outboard sides of the first and last IGRs. These may be blocked by increasing the body doping in regions surrounding the remaining leakage paths. The IGRs have substantially no source regions.

Power MOSFET current sense structure and method

A device includes a semiconductor substrate having a surface, a trench in the semiconductor substrate extending vertically from the surface, a body region laterally adjacent the trench, spaced from the surface, having a first conductivity type, and in which a channel is formed during operation, a drift region between the body region and the surface, and having a second conductivity type, a gate structure disposed in the trench alongside the body region, recessed from the surface, and configured to receive a control voltage is applied to control formation of the channel, and a gate dielectric layer disposed along a sidewall of the trench between the gate structure and the body region. The gate structure and the gate dielectric layer have a substantial vertical overlap with the drift region such that electric field magnitudes in the drift region are reduced through application of the control voltage.

Bidirectional trench FET with gate-based resurf

Semiconductor device structures and related fabrication methods are provided. An exemplary semiconductor device structure () includes a trench gate structure (), a lateral gate structure (), a body region () having a first conductivity type, a drain region () and first and second source regions () having a second conductivity type. The first and second source regions () are formed within the body region (). The drain region () is adjacent to the body region () and the first source region () is adjacent to the trench gate structure (), wherein a first portion of the body region () disposed between the first source region () and the drain region () is adjacent to the trench gate structure (). A second portion of the body region () is disposed between the second source region () and the drain region (), and the lateral gate structure () is disposed overlying the second portion of the body region ().

Semiconductor device and related fabrication methods

A power MOSFET includes a semiconductor substrate with an upper surface, a cavity of a first depth in the substrate whose sidewall extends to the upper surface, a dielectric liner in the cavity, a gate conductor within the dielectric liner extending to or above the upper surface, body region(s) within the substrate of a second depth, separated from the gate conductor in a lower cavity region by first portion(s) of the dielectric liner of a first thickness, and source region(s) within the body region(s) extending to a third depth that is less than the second depth. The source region(s) are separated from the gate conductor by a second portion of the dielectric liner of a second thickness at least in part greater than the first thickness. The dielectric liner has a protrusion extending laterally into the gate conductor away from the body region(s) at or less than the third depth.

Power MOSFET structure and method

A method is used to form a vertical MOS transistor. The method utilizes a semiconductor layer. An opening is etched in the semiconductor layer. A gate dielectric is formed in the opening that has a vertical portion that extends to a top surface of the first semiconductor layer. A gate is formed in the opening having a major portion laterally adjacent to the vertical portion of the gate dielectric and an overhang portion that extends laterally over the vertical portion of the gate dielectric. An implant is performed to form a source region at the top surface of the semiconductor layer while the overhang portion is present.

Method for forming a vertical MOS transistor

A semiconductor component includes a substrate () having a surface, a channel region () located in the substrate, a non-electrically conductive region () substantially located below a substantially planar plane defined by the surface of the substrate, a drift region () located in the substrate and between the channel region and the non-electrically conductive region, and an electrically floating region () located in the substrate and contiguous with the non-electrically conductive region.

Semiconductor component and method of manufacturing

A power MOSFET device (40) includes one or more localized regions of doping (61,62,63) formed in a more lightly doped semiconductor layer (42). The one or more localized regions of doping (61,62,63) reduce inherent resistances between the source regions (47,48) and the drain region (41) of the device. The one or more localized regions of doping (61,62,63) are spaced apart from the body regions (44,46) to avoid detrimentally impacting device breakdown voltage. In an alternative embodiment, a groove (122) or trench (152) design is incorporated to reduce JFET resistance (34). In a further embodiment, a gate dielectric layer having a thick portion (77,97,128,158) and thin portions (76,126,156) is incorporated to enhance switching characteristics and/or breakdown voltage.

Power MOSFET device having low on-resistance and method

A method for forming a semiconductor device includes forming insulated gate regions (122,222) on a substrate (26) using a first photo-masking step, forming a base region (47) through an opening (143) between the insulated gate regions (122,222), and forming a source region (152) within the base region (47). Next, a protective layer (61) is formed and selectively patterned using a second photo-masking step to form an opening (62) within the first opening (143) and an opening (63) above one of the insulated gate regions (122). Next, a portion (66) of the substrate (26) and a portion (67) of the insulated gate region (122) are removed. Ohmic contacts (74,76) are then formed and patterned using a third photo-masking step. Additionally, a termination structure (81) is described.

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Tempe, AZ, United States of America

Edouard D De Fresart