Infineon Technologies Ag

Edmund Riedl

Alexander Heinrich

Ralf Otremba

Wu Hu Li

Joachim Mahler

Johannes Lodermeyer

Werner Josef Reiss

Steffen Jordan

Khalil Hosseini

Manfred Schneegans

Wolfgang Schober

Ivan Nikitin

Manfred Mengel

Evelyn Napetschnig

Thomas Behrens

Stefan Miethaner

Oliver Eichinger

Ivan Galesic

Markus Leicht

Lim Fong

Steffen Orso

Thorsten Meyer

Georg Meyer-Berg

Irmgard Escher-Poeppel

Wolfgang Lehnert

Thorsten Scharf

Mathias Vaupel

Werner Robl

Stefan Paulus

Stefan Woehlert

Johann Gatterbauer

Karsten Guth

Ralf Wombacher

Konrad Roesl

Reinhard Pufall

Bernd Betz

Christof Matthias Schilz

Robert Bergmann

Stefan Schwab

Harry Walter Sax

Norbert Mais

Klaus Schmidt

Patrick Schwarz

Thomas Horedt

Ali Mazloum-Nejadari

Fee Hoon Wong

Steffan Jordan

Verena Muhr

Stefan Wohlert

Dieter Lachman

A method of manufacturing a package includes forming an adhesion promoter on at least part of an electronic component. The adhesion promoter is a morphological adhesion promoter including a morphological structure having a plurality of openings. The method further includes at least partially encapsulating the electronic component with an inorganic encapsulant with the adhesion promoter in between. The adhesion promoter enhances adhesion between at least part of the electronic component and the encapsulant.

Method of manufacturing a package having an adhesion promoter

A structure includes a first sub-structure and a second sub-structure coupled with the first sub-structure and being a composite including filler particles in a matrix. A surface of the first sub-structure has a surface profile with first elevations and first recesses configured to enable at least part of the filler particles to at least partially enter the first recesses to thereby form an interlayer including the first elevations of the first sub-structure and filler particles in the matrix of the second sub-structure.

Interlayer of sub-structure having elevations and further sub-structure with filler particles in recesses between the elevations

A package includes an electronic component, an inorganic encapsulant encapsulating at least part of the electronic component, and an adhesion promoter between at least part of the electronic component and the encapsulant.

Inorganic encapsulant for electronic component with adhesion promoter

A method of making a semiconductor including soldering a conductor to an aluminum metallization is disclosed. In one example, the method includes substituting an aluminum oxide layer on the aluminum metallization by a substitute metal oxide layer or a substitute metal alloy oxide layer. Then, substitute metal oxides in the substitute metal oxide layer or the substitute metal alloy oxide layer are at least partly reduced. The conductor is soldered to the aluminum metallization using a solder material.

Soldering a conductor to an aluminum metallization

A method of forming a layer structure is provided. The method may include plasma-treating a metal surface with a hydrogen-containing plasma, thereby forming nucleophilic groups over the metal surface, and forming an organic layer over the metal surface, wherein the organic layer comprises silane and is covalently bonded to the nucleophilic groups.

Method of forming a layer structure, layer structure, method of forming a contact structure, method of forming a chip package, and chip package

A chip arrangement including a chip comprising a chip back side; a back side metallization on the chip back side, the back side metallization including a plurality of layers; a substrate comprising a surface with a metal layer; a zinc-based solder alloy configured to attach the back side metallization to the metal layer, the zinc-based solder alloy having by weight 8% to 20% aluminum, 0.5% to 20% magnesium, 0.5% to 20% gallium, and the balance zinc; wherein the metal layer is configured to provide a good wettability of the zinc-based solder alloy on the surface of the substrate. The plurality of layers may include one or more of a contact layer configured to contact a semiconductor material of the chip back side; a barrier layer; a solder reaction, and an oxidation protection layer configured to prevent oxidation of the solder reaction layer.

Chip arrangements

A metallic interconnection and a semiconductor arrangement including the same are described, wherein a method of manufacturing the same may include: providing a first structure including a first metallic layer having protruding first microstructures; providing a second structure including a second metallic layer having protruding second microstructures; contacting the first and second microstructures to form a mechanical connection between the structures, the mechanical connection being configured to allow fluid penetration; removing one or more non-metallic compounds on the first metallic layer and the second metallic layer with a reducing agent that penetrates the mechanical connection and reacts with the one or more non-metallic compounds; and heating the first metallic layer and the second metallic layer at a temperature causing interdiffusion of the first metallic layer and the second metallic layer to form the metallic interconnection between the structures.

Metallic interconnect, a method of manufacturing a metallic interconnect, a semiconductor arrangement and a method of manufacturing a semiconductor arrangement

A connection member for connecting an electronic chip, wherein the connection member comprises a bulk body, and a coating at least partially coating the bulk body and comprising a material having higher electric and higher thermal conductivity than the bulk body, wherein a ratio between a thickness of the coating and a thickness of the bulk body is at least 0.0016 at at least a part of the connection member.

Connection member with bulk body and electrically and thermally conductive coating

A solder alloy is providing, the solder alloy including zinc, aluminum, magnesium and gallium, wherein the aluminum constitutes by weight 8% to 20% of the alloy, the magnesium constitutes by weight 0.5% to 20% of the alloy and the gallium constitutes by weight 0.5% to 20% of the alloy, the rest of the alloy including zinc.

Solder alloys and arrangements

A method of fabricating a semiconductor device. One embodiment provides a metal carrier. A semiconductor chip is provided. A porous layer is produced at a surface of at least one of the carrier and the semiconductor chip. The semiconductor chip is placed on the carrier. The resulting structure is heated until the semiconductor chip is attached to the carrier.

Method of fabricating a semiconductor device

A semiconductor package includes a semiconductor component including a circuit carrier with a plurality of inner contact pads, a semiconductor chip, and a plurality of electrical connections. An adhesion promotion layer is disposed on at least areas of the semiconductor component and a plastic encapsulation material encapsulates at least the semiconductor chip, the plurality of electrical connections and the plurality of the inner contact pads. Surface regions of the semiconductor component are selectively activated.

Semiconductor package and method of assembling a semiconductor package

A bonding material including a meltable joining material and a plurality of heterostructures distributed throughout the meltable joining material, the heterostructures comprising at least a first material and a second material capable of conducting a self-sustaining exothermic reaction upon initiation by an external energy to generate heat sufficient to melt the meltable joining material.

Bonding material with exothermically reactive heterostructures

Growing community of inventors

Wald, Germany

Edmund Riedl