Globalfoundries Inc.

Eastman-kodak Company

Globalfoundries U.S. Inc.

Truesense Imaging, Inc.

Semiconductor Components Industries, LLC

Edmund Kenneth Banghart

Eric Gordon Stevens

Xusheng Kevin Wu

Hung Q Doan

Min-Hwa Chi

Shesh Mani Pandey

Constantine N Anagnostopoulos

Hong Yu

Jagar Singh

Yanxiang Liu

Katherina E Babich

Alexander M Derrickson

George Robert Mulfinger

Ryan W Sporer

Madhav Mehra

Edward T Nelson

Xinyuan Dou

James P Lavine

Alexander Lee Martin

Sandeep Gaan

Shishir K Ray

Bruce C Burkey

Ashish Kumar Jha

Oscar Restrepo

Mitsuhiro Togo

Sheldon Meyers

Ronald M Gluck

William F DesJardin

Dongil Choi

Nisha Pillai

Kyle Jung

Md Khaled Hassan

William Taylor

Hung Quoc Doan

Structures for an array of non-volatile memory cells and methods of forming a structure for an array of non-volatile memory cells. An active region of a substrate includes a first section having a side edge and a second section extending laterally from the side edge. The first section of the active region has a first length dimension in a direction parallel to the first side edge. The second section has a second length dimension in the direction parallel to the first side edge. The second length dimension is less than the first length dimension. A fin is positioned on the substrate in the second section of the active region. A gate structure extends over the fin and the second section of the active region.

Non-volatile memory cell arrays with a sectioned active region and methods of manufacturing thereof

Structures for a heterojunction bipolar transistor and methods of forming a structure for a heterojunction bipolar transistor. A first portion of a first semiconductor layer defines an emitter, a first portion of a second semiconductor layer defines a collector, and a base includes respective second portions of the first and second semiconductor layers that are laterally positioned between the first portion of the first semiconductor layer and the first portion of the second semiconductor layer. The first portion of the first semiconductor layer has a first thickness, and the first portion of the second semiconductor layer has a second thickness that is greater than the first thickness. The first portion and the second portion of the first semiconductor layer adjoin at a first junction having the first thickness. The first portion and the second portion of the second semiconductor layer adjoin at a second junction having the second thickness.

Lateral heterojunction bipolar transistors with asymmetric junctions

The present disclosure relates to semiconductor structures and, more particularly, to selective shallow trench isolation (STI) fill material for stress engineering in semiconductor structures and methods of manufacture. The structure includes a single diffusion break (SDB) region having at least one shallow trench isolation (STI) region with a stress fill material within a recess of the at least one STI region. The stress fill material imparts a stress on a gate structure adjacent to the at least one STI region.

Selective shallow trench isolation (STI) fill for stress engineering in semiconductor structures

A method of forming a FinFET fin with low-doped and a highly-doped active portions and/or a FinFET fin having tapered sidewalls for Vt tuning and multi-Vt schemes and the resulting device are provided. Embodiments include forming an Si fin, the Si fin having a top active portion and a bottom active portion; forming a hard mask on a top surface of the Si fin; forming an oxide layer on opposite sides of the Si fin; implanting a dopant into the Si fin; recessing the oxide layer to reveal the active top portion of the Si fin; etching the top active portion of the Si fin to form vertical sidewalls; forming a nitride spacer covering each vertical sidewall; recessing the recessed oxide layer to reveal the active bottom portion of the Si fin; and tapering the active bottom portion of the Si fin.

Fin structures and multi-Vt scheme based on tapered fin and method to form

Semiconductor structures and methods of fabrication are provided, with one or both of an extended source-to-channel interface or an extended drain-to-channel interface. The fabrication method includes, for instance, recessing a semiconductor material to form a cavity adjacent to a channel region of a semiconductor structure being fabricated, the recessing forming a first cavity surface and a second cavity surface within the cavity; and implanting one or more dopants into the semiconductor material through the first cavity surface to define an implanted region within the semiconductor material, and form an extended channel interface, the extended channel interface including, in part, an interface of the implanted region within the semiconductor material to the channel region of the semiconductor structure. In one embodiment, the semiconductor structure with the extended channel interface is a FinFET.

Semiconductor structure(s) with extended source/drain channel interfaces and methods of fabrication

Semiconductor substrates and methods for processing semiconductor substrates are provided. A method for processing a semiconductor substrate includes providing a semiconductor substrate having an outer edge, a central region, and a peripheral region between the outer edge and the central region. The semiconductor substrate also has an upper surface. The method includes forming an amorphous material over the upper surface of the semiconductor substrate in the peripheral region. Also, the method includes irradiating the upper surface of the semiconductor substrate, wherein the amorphous material inhibits cracking at the outer edge of the semiconductor substrate.

Semiconductor substrates and methods for processing semiconductor substrates

Methods are provided for fabricating a fin-type field effect transistor(s), having a channel region within a fin. The methods include: establishing a protective material above an upper surface of the fin, and an isolation material adjacent to at least one sidewall of the fin, the isolation material being recessed down from the upper surface of the fin, for instance, for approximately a height of the channel region within the fin; and providing a punch-through stop dopant region within the fin below the channel region, the providing including implanting a punch-through stop dopant into the isolation material and laterally diffusing the punch-through stop dopant from the isolation material into the fin to form the punch-through stop region within the fin beneath the channel region.

Fabricating fin-type field effect transistor with punch-through stop region

A lateral overflow drain and a channel stop are fabricated using a double mask process. Each lateral overflow drain is formed within a respective channel stop. Due to the use of two mask layers, one edge of each lateral overflow drain is aligned, or substantially aligned, with an edge of a respective channel stop.

Lateral overflow drain and channel stop regions in image sensors

Method of forming lateral overflow drain and channel stop regions in image sensors

An image sensor having an anti-blooming structure, where the image sensor comprises a substrate of a first conductivity type; a dielectric having a first thin portion and a second thick portion; a buried channel of the second conductivity type within the substrate substantially spanning the first thin portion; and a lateral overflow drain region of the second conductivity type disposed substantially in its entirety spanning a portion of the second thick portion for collecting excess photogenerated charges for preventing blooming.

Lateral overflow drain, anti-blooming structure for CCD devices having improved breakdown voltage

By introducing an n-type drain implant substantially below the surface of the p-type substrate of a full frame image sensor, then enclosing the drain on the bottom and the sides with a deep p-type implant, and accumulating the surface with a shallow p-type implant, with all implantations performed through the same mask aperture, the blooming control, channel stop, and dark current suppression features of the imager are compressed, increasing the fill factor, facilitating pixel miniaturization, and therefore enabling high resolution imaging applications.

Compact isolation and antiblooming structure for full-frame CCD image

A charge-coupled device having an improved charge-transfer efficiency over a broad temperature range. The device comprises a substrate of semiconductor material of one conductivity type; a first buried channel formed in the substrate and of a conductivity type opposite to that of the substrate; a second buried channel of a conductivity type opposite to that of the substrate formed in the same region of the substrate as the first buried channel and having a greater depth of penetration into the substrate than the first buried channel; compensated regions formed at intervals in the buried channels providing a means for containing individual packets of charge and shaped for inducing a narrow channel effect and for producing a fringing electric field in a direction of charge transfer in uncompensated buried channel regions; electrode gates associated with each pair of adjoining compensated and uncompensated regions in the device; and means for clocking the electrodes for causing a string of charge packets to be transferred through the device.

Charge-coupled device having an improved charge-transfer efficiency over

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Pittsford, NY, United States of America

Edmund Kenneth Banghart