International Business Machines Corporation

Edith Lattard

Renzo Maccagnan

Philippe Coronel

There is disclosed an improved method of forming the spacer which isolates the gate conductor from the metal contact with the diffusion (source/drain) region of each array transfer transistor for all memory cells of a DRAM chip. According to the method there is provided a structure consisting of a silicon substrate having a diffusion region formed therein and gate conductor (GC) lines formed thereon. Then, an oxynitride layer and a silicon nitride (Si N ) layer are conformally deposited in sequence onto the structure by LPCVD in the same tool for total clusterization. Next, the structure is anisotropically dry etched with a chemistry that is Si N /oxynitride selective to expose the oxynitride layer between the GC lines and the upper portion thereof in a one step process to form the Si N spacers. Still in accordance with the invention, the above method finds a valuable application in the fabrication of borderless metal contacts in DRAM chips wherein the risk of having potential an electrical short between the gate conductor and the metal contact is substantially eliminated.

Method of forming insulating spacers in DRAM chips

A conventional initial deep trench structure consists of a patterned Si,N,pad layer coated silicon substrate with deep trenches formed therein. The trenches are partially filled with doped polysilicon (POLY1). A dielectric film is interposed between said polysilicon fill and the substrate to create the storage capacitor. A TEOS SiO,collar layer conformally coats the upper portion of the structure. Now, the TEOS SiO,is dry etched in a two-step process performed in the same RIE reactor. In the first step, the TEOS SiO,is etched at least 6 times faster than the Si,N,(stopping on the Si,N,pad layer). In the second step, the operating conditions ensure a partially isotropic dry etch, preferably with twice the power and 1.25 times the pressure, thus providing a vertical etch rate 6&times; the horizontal rate. As a result of this step, the upper part of the silicon substrate in the trench is exposed without damages. Next, N-type dopant is implanted in the upper portion of the silicon substrate to create a doped region. The trench is filled with a layer of doped polysilicon (POLY2) which is planarized by chemical-mechanical polishing down to approximately the Si,N,pad layer surface and finally recessed down to a depth level substantially coplanar with the silicon surface substrate to create a POLY2 stud. The buried strap is formed by the doped region and POLY2 stud. The above method presents significant advantages in terms of product reliability, throughput improvements and process flow simplification.

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Trets, France

Edith Lattard