Imec Vzw

Interuniversitair Microelektronica Centrum (imec)

Nxp B.v.

Interuniversitair Micorelektronica Centrum (imec, Vzw)

Eddy Kunnen

Johannes Josephus Theodorus Marinus Donkers

Petrus Hubertus Cornelis Magnee

Serge Vanhaelemeersch

Nadine Collaert

Simone Severi

Koen Martens

Vasile Paraschiv

Steven Demuynck

Jürgen Bömmels

Francois Igor Neuilly

Laure Elisa Carbonell

Twan Bearda

Examples include a method for forming an intermediate in the fabrication of a field-effect transistor sensor, the method comprising: providing a substrate having a substrate region comprising a gate dielectric thereon and optionally a nanocavity therein, providing a sacrificial element over the substrate region, providing one or more layers having a combined thickness of at least 100 nm over the sacrificial element, opening an access to the sacrificial element through the one or more layers, and optionally selectively removing the sacrificial element, thereby opening a sensor cavity over the substrate region; wherein the sacrificial element is removable by oxidation and wherein selectively removing the sacrificial element comprises an oxidative removal.

Protecting a substrate region during fabrication of a FET sensor

A method is provided for blocking a portion of a longitudinal through-hole during manufacture of a semiconductor structure, comprising the steps of: forming a stack comprising a hard mask comprising at least one trench, and a first coating filling the at least one trench and coating the hard mask, wherein the first coating comprises one or more materials that can be etched selectively with respect to a second coating; etching at least one vertical via in the first coating directly above the portion of the trench in such a way as to remove the first coating over at least a fraction of the depth of the trench, filling the at least one via with the second coating material, and removing the first coating selectively with respect to the second coating from at least the one or more longitudinal through-holes in such a way as to leave in place any of the first coating present directly underneath the second coating.

Method for blocking a trench portion

A method for removing oxide selective to a material comprising at least silicon and at least nitrogen is disclosed, the method comprising providing in a reactor a structure having a surface comprising a region, wherein said region comprises a material comprising at least silicon and at least nitrogen, providing on said structure an oxide layer overlying at least a part of said region, and removing said oxide layer selective to said material by etching, thereby exposing at least a part of said at least overlaid part of said region, wherein said etching is done only by providing an etchant gas comprising boron, whereby a voltage bias lower than 30 V is applied to the structure.

Method for selective oxide removal

A method for forming an epitaxial base layer in a bipolar device. The method comprises the steps of: providing a structure having a field isolation oxide region () adjacent to an active silicon region (); forming a silicon nitride/silicon stack () above the field isolation oxide region (), wherein the silicon nitride/silicon stack () includes a top layer of silicon () and a bottom layer of silicon nitride (); performing an etch to the silicon nitride/silicon stack () to form a stepped seed layer, wherein the top layer of silicon is etched laterally at the same time the bottom layer of silicon nitride is etched; and growing an Si/SiGe/Si stack () over the stepped seed layer and active region ().

Method to reduce seedlayer topography in BICMOS process

A method for forming deep trench or via airgaps in a semiconductor substrate is disclosed comprising the steps of patterning a hole in the substrate, partly fill said hole with a sacrificial material (e.g. poly-Si), depositing spacers on the sidewalls of the unfilled part of the hole (e.g. TEOS) to narrow the opening, removing through said narrowed opening the remaining part of the sacrificial material (e.g. by isotropic etching) and finally sealing the opening of the airgap by depositing a conformal layer (TEOS) above the spacers. The method of forming an airgap is demonstrated successfully for use as deep trench isolation structures in BiCMOS devices.

Formation of deep trench airgaps and related applications

A method for forming deep via airgaps in a semiconductor substrate is disclosed comprising the steps of patterning a hole in the substrate, partly fill said hole with a sacrificial material (e.g. poly-Si), forming spacers on the sidewalls of the unfilled part of the hole (e.g. TEOS) to narrow the opening, removing through said narrowed opening the remaining part of the sacrificial material (e.g. by isotropic etching) and finally sealing the opening of the airgap by depositing a conformal layer (TEOS) above the spacers. The method of forming a deep via airgap is used to create wafer to wafer vertical stacking. After completion of conventional FEOL and BEOL processing the backside of the wafer will be thinned such that the deep via airgap is opened and conductive material can be deposited within said (airgap) via opening and a through wafer or deep via filled with conductive material is created.

Formation of deep via airgaps for three dimensional wafer to wafer interconnect

A method for forming macropores in a substrate is disclosed. On a substrate a pattern of submicron features is formed. This pattern is covered with a layer, which is preferably selectively removable with respect to the substrate and the submicron features. This cover layer is removed until the submicron features are exposed. The submicron features are then etched selectively to the cover layer, thereby creating a pattern of submicron openings in this cover layer. The patterned cover layer is used as a hardmask to etch macropores in the substrate.

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Kessel-lo, Belgium

Eddy Kunnen