Micron Technology Incorporated

Round Rock Research, LLC

Ebrahim H Hargan

Layne G Bunker

Gregory A King

Dragos Dimitriu

Brent Keeth

Troy A Manning

Chris G Martin

A stack of vertically-connected, horizontally-oriented integrated circuits (ICs) may have electrical connections from the front side of one IC to the back side of another IC. Electrical signals may be transferred from the back side of one IC to the front side of the same IC by means of through substrate vias (TSVs), which may include through silicon vias. Electronic apparatus, systems, and methods may operate to test and/or replace defective TSVs. Additional apparatus, systems and methods are disclosed.

Apparatus and methods for through substrate via test

A memory system and method using at least one memory device die stacked with and coupled to a logic die by interconnects, such as through silicon vias. One such logic die includes an ECC system generating error checking and correcting ('ECC) bits corresponding to write data. The write data are transmitted to the memory device dice in a packet containing a serial burst of a plurality of parallel data bits. The ECC bits are transmitted to the memory device dice using through silicon vias that are different from the vias through which data are coupled. Such a logic die could also include a data bus inversion ('DBI') system encoding the write data using a DBI algorithm and transmitting to the memory device dice DBI bits indicating whether the write data have been inverted. The DBI bits are transmitted using through silicon vias that are shared with the ECC bits when they are unused for transferring the ECC bits.

Memory system and method using a memory device die stacked with a logic die using data encoding, and system using the memory system

Various embodiments include apparatus and methods having circuitry to test continuity of conductive paths coupled to dice arranged in a stack. In at least one of these embodiments, a method includes electrically coupling each of the conductive paths to at least one of a first supply node and a second supply node. One of the conductive paths includes conductive material inside a via that can extend at least partly through a die among the dice in the stack. The method also includes receiving signals from the conductive paths, and determining continuity of the conductive paths based on the signals without using a boundary scan.

Method for manufacturing a stacked device conductive path connectivity

Signal transmission apparatus, systems, and methods are disclosed. In various embodiments, a signal transmission system includes a transmission network having signal paths configured to communicate signals from an input to an output, a first steering network coupled to the input that communicates with the transmission network, and a second steering network coupled to the output that communicates with the transmission network. A steering control network that receives error signals corresponding to an inoperable signal path and that generates steering signals directed to the first steering network and the second steering network is included, so that the steering signals shift signals to an alternate, operable signal path from the inoperable signal path. Additional apparatus, systems, and methods are disclosed.

Redundant signal transmission

Data digits and correction digits are received in each of a number of integrated circuit (IC) devices. Apparatus, systems, and methods are disclosed that operate to check the data digits for error in each IC device according to an algorithm associated with the IC device, the algorithm being different for each IC device. Each IC device will act in response to the data digits if no error is detected in the data digits. Additional apparatus, systems, and methods are disclosed.

Multiple device apparatus, systems, and methods

In one aspect of the invention, a method of reducing intersymbol interference on a signal line is disclosed. A state machine records previous bits that were transmitted over the line. If the bit on the line has been static for several clock cycles, the slew rate will be increased to facilitate correct reading of the bit for the next clock cycle. If the bit on the line has been dynamic for the previous bits, the slew rate will be a lower slew rate to avoid crosstalk between neighboring lines.

Devices and methods for controlling a slew rate of a signal line

Various embodiments include apparatus and methods having circuitry to test continuity of conductive paths coupled to dice arranged in a stack.

Stacked device conductive path connectivity

A memory malfunction prediction system and method, such as those that sequentially stress each row of memory cells in an array by decreasing the refresh rate of the row. Prior to doing so, the data stored in the row can be copied to a holding row, and a CRC value for the data can be generated and stored. After the test, the data stored in the row being tested can be read, and a CRC value for the data can then be generated. This after test CRC value can be compared to the stored pre-test CRC value. In the event of a match, the row can be considered to be functioning properly, and the next row can then be tested. If the CRC values do not match, a predicted malfunction of the row can be considered to exist, and corrective action can be taken, such as by repairing the row by substituting a redundant row of memory cells.

Growing community of inventors

Boise, ID, United States of America

Ebrahim H Hargan