Taiwan Semiconductor Manufacturing Comp. Ltd.

Ebin Liao

Wen-Chih Chiou

Tsang-Jiuh Wu

Chen-Hua Douglas Yu

Li-Hsien Huang

Cheng-Hung Chang

Chia-Lin Yu

Chun Hua Chang

Hsiang-Yi Wang

Darryl Kuo

Ku-Feng Yang

Yi-Hsiu Chen

Chia-Yin Chen

Fu-Kang Tien

Yang-Chih Hsueh

Yan-Zuo Tsai

Shin-Puu Jeng

Yung-Chi Lin

Yuan-Hung Liu

Hong-Ye Shih

Yen-Hung Chen

Jia-Ling Ko

Yin-Hua Chen

The disclosure provides a method of forming a package structure, and the method includes: bonding a die to a wafer; performing a thinning process on the die, wherein the die has a first total thickness variation (TTV) after performing the thinning process; forming a dielectric layer on the wafer to cover sidewalls and a top surface the die; performing a first removal process to remove a first portion of the dielectric layer and expose the top surface of the die; and performing a second removal process to remove a second portion of the dielectric layer and a portion of the die, wherein after performing the second removal process, the die has a second TTV less than the first TTV.

Package structure and method of forming the same

A semiconductor component includes a substrate having an opening. The semiconductor component further includes a first dielectric liner in the opening, wherein the first dielectric liner having a thickness Tat a first end of the opening, and a thickness Tat a second end of the opening, and Ris a ratio of Tto T. The semiconductor component further includes a second dielectric liner over the first dielectric liner, wherein the second dielectric liner having a thickness Tat the first end of the opening, a thickness Tat the second end of the opening, Ris a ratio of Tto T, and Ris greater than R.

Semiconductor component having through-silicon vias

A bonding apparatus includes a chuck and a bonding head. The chuck is configured to carry a plurality of substrates to be bonded. The bonding head has a cavity facing the chuck and includes a divider, at least one pneumatic component and a diaphragm. The divider is disposed in the cavity and dividing the cavity into a plurality of compartments. The at least one pneumatic component is disposed in at least one of the compartments. The diaphragm covers the cavity and is disposed between the at least one pneumatic component and the chuck.

Bonding apparatus and method of bonding substrates

A method and apparatus for bonding semiconductor devices are disclosed. In an embodiment, the method may include attaching a first die to a flip head of a flip module, flipping the first die with the flip module, removing the first die from the flip module after flipping the first die, inspecting the flip head of the flip module for contamination after removing the first die, cleaning the flip head with an in situ cleaning module after inspecting the flip head, and attaching a second die to the flip head after cleaning the flip head.

Method and apparatus for bonding semiconductor devices

A method of making a semiconductor component includes etching a substrate to define an opening. The method further includes depositing a first dielectric liner in the opening, wherein the first dielectric liner has a first stress. The method further includes depositing a second dielectric liner over the first dielectric liner, wherein the second dielectric liner has a second stress, and a direction of the first stress is opposite a direction of the second stress. The method further includes depositing a conductive material over the second dielectric liner.

Method of making a semiconductor component having through-silicon vias

Semiconductor devices, methods of manufacture thereof, and capacitors are disclosed. In some embodiments, a semiconductor device includes a first capacitor and a protection device coupled in series with the first capacitor. A second capacitor is coupled in parallel with the first capacitor and the protection device.

Semiconductor devices, methods of manufacture thereof, and capacitors

Provided is a 3DIC structure includes a wafer, a die and a dielectric layer. The die is over and bonded to the wafer. The dielectric layer is over the wafer and aside the die, covering sidewalls of the die. A total thickness variation (TTV) of the die is less than 0.8 &#x3bc;m.

Three-dimensional integrated circuit structure and method of manufacturing the same

A semiconductor component includes a semiconductor substrate having an opening A first dielectric liner having a first compressive stress is disposed in the opening. A second dielectric liner having a tensile stress is disposed on the first dielectric liner. A third dielectric liner having a second compressive stress disposed on the second dielectric liner.

Semiconductor component having through-silicon vias and method of manufacture

A device including a first dielectric layer on a semiconductor substrate, a gate electrode formed in the first dielectric layer, and a through-substrate via (TSV) structure penetrating the first dielectric layer and extending into the semiconductor substrate. The TSV structure includes a conductive layer, a diffusion barrier layer surrounding the conductive layer and an isolation layer surrounding the diffusion barrier layer. A capping layer including cobalt is formed on the top surface of the conductive layer of the TSV structure.

Methods for forming a device having a capped through-substrate via structure

Device with capped through-substrate via structure

A structure includes a substrate, and an interconnect structure over the substrate. The structure further includes a through-substrate-via (TSV) extending through the interconnect structure and into the substrate, the TSV comprising a conductive material layer. The structure further includes a dielectric layer having a first portion over the interconnect structure and a second portion within the TSV, wherein the first portion and the second portion comprise a same material. The conductive material layer includes a first section separated from substrate by the second portion of the dielectric layer. The conductive material layer further includes a second section over a top surface of the second portion of the dielectric layer. The conductive material layer further includes a third section over the second section, wherein the third section has a width greater than a width of the second section.

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Xinzhu, Taiwan

Ebin Liao