Freescale Semiconductor,inc.

Nxp USA, Inc.

Dwight Lee Daniels

Stephen Ryan Hooper

Alan J Magnus

Michael B Vincent

Scott M Hayes

Justin Eugene Poarch

William G McDonald

James MacDonald

Chunlin C Xia

Robert F Steimle

Chad S Dawson

Mark Edward Schlarmann

Akhilesh Kumar Singh

Darrel R Frear

Gary Carl Johnson

Jeroen Johannes Maria Zaal

Yufu Liu

Fengyuan Li

Cheong Chiang Ng

Paul Southworth

Veera M Gunturu

Pamela A O'Brien

Namrata Kanth

Thomas Cobb Speight

Ryan Hooper

An electronic device substrate with a substantially planar surface formed from an electrically non-conductive material is provided with one or more metalized pads on the substantially planner surface. Each of the one or more metalized pads is surrounded by and coplanar with the first electrically nonconductive material along an outer boundary of the metalized pad. The metalized pad is patterned such that portions of the metalized pad form metalized fingers that extend radially from the outer boundary of the metalized pad in an interdigitated arrangement with the first electrically nonconductive material. The metalized pad has a solderable surface.

Patterned and planarized under-bump metallization

A semiconductor device includes a substrate, an IC die mounted on the substrate, packaging encapsulant on the substrate, a cavity in the packaging encapsulant, a conductive lid attached to the packaging encapsulant over the IC die, an electrical ground path in the substrate, and a first conductive structure in the cavity. The first conductive structure includes a first end electrically coupled to the conductive lid and a second end electrically coupled to the electrical ground path.

Grounding lids in integrated circuit devices

Embodiments for a packaged semiconductor device and methods of making are provided herein, where a packaged semiconductor device includes a package body having a recess in which a pressure sensor is located; a polymeric gel within the recess that vertically and laterally surrounds the pressure sensor; and a media shield including at least one metal layer on a top surface of the polymeric gel, wherein the media shield and the polymeric gel are sufficiently flexible to transmit pressure to the pressure sensor.

Media shield with EMI capability for pressure sensor

A packaged semiconductor device includes: a substrate; an semiconductor die attached to a top surface of the substrate; a mold body surrounding the semiconductor die; a tiered through mold via (TMV) comprising: a first recess having a recessed surface within the mold body at a first depth, and a second recess from the recessed surface to a second depth that exposes a ground contact area on a bonding area on the top surface of the substrate, wherein the first depth is greater than the second depth; and a metal shielding layer formed on a top surface of the mold body to form a shielded mold body, wherein the metal shielding layer makes direct contact with at least one sidewall of the first recess, with at least a portion of the recessed surface, with at least one sidewall of the second recess, and with the ground contact area.

High aspect ratio connection for EMI shielding

Embodiments of a packaged semiconductor device are provided, which includes a flag of a lead frame having a top surface and a bottom surface; a redistribution layer (RDL) structure formed on the top surface of the flag, the RDL structure including a first connection path having a first exposed bonding surface in a top surface of the RDL structure; and a first wirebond connected to the first exposed bonding surface and to a lead of the lead frame.

Lead frame having redistribution layer

A method of testing includes attaching a first and second die to first and second die sites of a lead frame and forming a plurality of wire bonds coupling a plurality of pins of the first die site to the first die and a plurality of pins of the second die site to the second die. The first and second die are encapsulated. An isolation cut is performed to isolate the plurality of pins of the first die site from the plurality of pins of the second die site, while maintaining electrical connection between the first tie bar of the first die site and the first tie bar of the second die site. The first and second die are tested while providing a first power supply source to the first and second die via the first tie bars. After testing, the dies sites are fully singulated to result in packaged IC device.

Devices and methods for testing integrated circuit devices

A device in which an electronic circuit positioned within a cavity of a package housing is encased by a bubble restrictor material, with a media resistant material overlaying the bubble restrictor material. The bubble restrictor material functions to inhibit the formation and growth of moisture-related bubbles within the material, including at the interfaces of the material and surfaces within the package housing. The media resistant material is resistant to physical and chemical alterations by media within an external environment to which the device is exposed. The media resistant material and bubble resistant material function to transfer a sensed characteristic of the media to the electronic circuit.

Environmental sensor structure

A structure to improve saw singulation quality and wettability of integrated circuit packages () is assembled with lead frames () having half-etched recesses () in leads. In one embodiment, the structure is a lead frame strip () having a plurality of lead frames. Each of the lead frames includes a depression () that is at least partially filled with a material () prior to singulating the lead frame strip. In another embodiment, the structure is a semiconductor device package () that includes a semiconductor device encapsulated in a package body () having a plurality of leads (). Each lead has an exposed portion external to the package. There is recess () at a corner of each lead. Each recess has a generally concave configuration. Each recess is filled with a removable material ().

Semiconductor device package and method of manufacture

A method for protecting terminal elements on a wafer during wafer level fabrication processes entails applying a protective coating to the terminal elements prior to further processing operations. These processing operations may include back side grinding of the wafer and/or saw-to-reveal operations to expose the terminal elements from a cap wafer of a wafer structure. The protective coating can protect the terminal elements from potentially damaging contaminants, such as debris from the grinding or saw-to-reveal operations. Furthermore, the protective coating can protect the bond pads from coming into contact with a rapidly oxidizing environment when exposed to water. The protective coating may be a hot-water soluble thermoplastic material the melts from a solid form to a liquid form at a relatively low temperature to enable application of the protective coating in liquid form onto the terminal elements and clean removal of the protective coating from the terminal elements.

Method of bond pad protection during wafer processing

A structure and method to improve saw singulation quality and wettability of integrated circuit packages () assembled with lead frames () having half-etched recesses () in leads. A method of manufacturing lead frames includes providing a lead frame strip () having a plurality of lead frames. Each of the lead frames includes a depression () that is at least partially filled with a material () prior to singulating the lead frame strip.

Methods of manufacturing a flat-pack no-lead microelectronic package () coat exposed base metal at a cut end of a lead frame of the package with solder (). One method coats the exposed base metal with solder when the package is in a strip (). Another method coats the exposed base metal with solder after the package is singulated. As a result, all portions of leads of the package that may receive solder during mounting of the package to a printed circuit board are solder wettable. A solder wettable lead end () on the package facilitates formation of a solder fillet during mounting of the package.

Wettable lead ends on a flat-pack no-lead microelectronic package

A structure and method to improve saw singulation quality and wettability of integrated circuit packages () assembled with lead frames () having half-etched recesses () in leads. A method of forming a semiconductor device package includes providing a lead frame strip () having a plurality of lead frames. Each of the lead frames includes a depression () that is at least partially filled with a material () prior to singulating the strip.

Fabrication methods are provided for a sensor device packages. An exemplary fabrication method involves bonding a sensor structure and another structure using a sealing structure. The sealing structure surrounds a diaphragm region of the sensor structure and provides an airtight seal between the sensor structure and the other structure to establish a fixed reference pressure on one side of the diaphragm region.

Methods for fabricating sensor device package using a sealing structure

Apparatus and related fabrication methods are provided for a sensor device. The sensor device includes a sensor structure including a first portion having a sensing arrangement formed thereon and a second structure. A sealing structure is interposed between the sensor structure and the second structure, wherein the sealing structure surrounds the first portion of the sensor structure. The sealing structure establishes a fixed reference pressure on a first side of the first portion, and an opposing side of the first portion is exposed to an ambient pressure.

Sensor device with sealing structure

A semiconductor device includes a first cap wafer having a first opening extending through the first cap wafer, and a second cap wafer bonded to the first cap wafer, wherein the second cap wafer has a second opening extending through the second cap wafer, and wherein the first opening is misaligned with respect to the second opening. The second cap wafer is bonded to a device wafer, wherein a cavity is formed between the device wafer and the second cap wafer, and wherein the device wafer comprises at least one semiconductor device in the cavity. A vacuum sealing layer is formed over the first cap wafer, wherein the sealing layer vacuum seals the first opening.

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Phoenix, AZ, United States of America

Dwight Lee Daniels