Hewlett-Packard Company

Dwight Jaynes

Harold Wallace Dozier

Michael D Bienek

A system for testing an integrated circuit. The system includes a plurality of simultaneous switching output (SSO) cells with each of the plurality of simultaneous SSO cells including an output driver providing an output signal to a respective signal pin coupled to the integrated circuit, a toggle circuit toggling its output; a multiplexer selecting a signal for communication to the output driver to control output provided to the respective signal pin, an input signal line communicating an SSO enable signal to the multiplexer, wherein the multiplexer selects the toggled output for communication to the output driver when the SSO enable signal is asserted; and a signal pin that is coupled to each respective input signal line of the plurality of SSO cells.

Multipurpose test chip input/output circuit

The circuit to be used either to create a simultaneously switching outputs (SSO) event or to create a simultaneously switching inputs (SSI) event. The circuit uses a toggle register to generate a toggling signal and a signal line to operate logic to select the toggling signal as output from the circuit for the SSO event. The signal line is connected to an external pin. The circuit uses another signal line, also connected to an external pin, to disable or tristate the output driver that drives the I/O pin. This permits the circuit to receive input for the SSI event. Two chips, each having a plurality of such circuits, can be arranged so that one chip generates the SSO event and sends it to the second chip, which is configured to receive the SSI event. The circuit also has a pair of registers in a cascade arrangement to provide precise control of the output signal. The circuit has an additional register to disable the output driver and permit the circuit to receive input for a scan event.

The inventive system and method determines path delay of at least one test path of logic gates. The invention uses a toggle register to generate a toggling signal, that is sent out onto the path by a launch register. A capture register receives the signal from the other end of the path. A logic gate compares the received signal from a prior launched signal with an inverted launched signal. Since the signal is a toggling signal the prior received signal should be the same as an inverted launched signal. A latch register determines whether the logic gate has detected a match between inverted launched signal and the received signal from a prior launch signal within a predetermined time clock period. As the clock period is shortened, the launched signal will fail to traverse the path and be captured by the capture register within the clock period. This will cause a mis-match in the logic gate. The clock period at the point of mis-match is the delay time of the path. The invention can use two paths to produce a very accurate comparison of the delays on the two paths.

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Richardson, TX, United States of America

Dwight Jaynes