Agilent Technologies, Inc.

Ncr Corporation

Hyundai Electronics America, Inc.

At&t Global Information Solutions Company

Durbin L Seidel

William Richard Lawrence

Bradley D Pace

Donald M Bartlett

Ricky F Bitting

James F Patella

The present invention is directed to a method and apparatus for testing integrated circuit package devices using automatic testing equipment. The automatic testing equipment may be provided with a light source to enable the testing of image capture type integrated circuit devices. Alternatively, the automatic testing equipment may be provided with an imaging device, e.g., a camera, or both an imaging device and a light source to additionally enable the testing of display type integrated circuit devices.

Method for testing integrated circuit devices

Apparatus and method for testing integrated circuit devices

A CMOS motor drive for a disk drive spindle motor. The design of the drive circuit permits the integration of power electronics together with logic or other circuitry on a single integrated circuit wafer. For each motor phase the power electronics formed on the integrated circuit wafer includes a plurality of P-type and N-type MOSFET power transistor pairs and a plurality of corresponding output bonding pads; the drain terminals of each transistor pair being connected together to its corresponding output bonding pad. The wafer is enclosed in packaging which includes an output pin for providing an electrical connection to one phase of the disk drive spindle motor, and a plurality of bond wires corresponding to the plurality of output bonding pads, each bond wire providing an electrical connection between its corresponding bonding pad and the output pin. The transistor pairs and bond wires operate in parallel, each carrying an equivalent portion of the total current output presented at the output pin. The gate terminals of all the P-type MOSFET transistors are electrically connected together to a first control input; and the gate terminals of all the N-type MOSFET transistors are electrically connected together to a second control input. The source terminals of each of the P-type transistors are connected through corresponding bonding pads and bond wires to a first voltage source input pin. Similarly, the source terminals of each of the N-type transistors are connected through corresponding bonding pads and bond wires to a second voltage source input pin.

CMOS power fet driver including multiple power MOSFET transistors

An improved sample-and-hold circuit includes a first MOSFET transmission gate connected between an analog input voltage and a storage capacitor. The first transmission gate is constructed to have low on resistance and operates for a predetermined period of time to rapidly charge the capacitor to input voltage. A second, smaller MOSFET transmission gate having reduced charge injection characteristics is connected in parallel with the first gate. The second gate is turned on coincidentally with the first gate but remains on for a short period of time after the first gate has been switched off.

Sample-and-hold switch with low on resistance and reduced charge

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Fort Collins, CO, United States of America

Durbin L Seidel