Nexflash Technologies, Inc.

Dung Tran

Kyung Joon Han

Steve K Hsia

Steven W Longcor

Joo Weon Park

Jong Seuk Lee

Gyu-Wan Kwon

Dae Hyun Kim

A memory array contains memory cells designed to be erased using Fowler-Nordheim (&ldquo;FN&rdquo;) tunneling through the channel area, and programmed using either channel hot electron injection (&ldquo;CHE&rdquo;) or channel-initiated secondary electron injection (&ldquo;CISEI&rdquo;). To reduce disturbance of the floating gate potential of unselected memory cells during programming operations and read operations, the unselected word lines are brought to a negative potential rather than ground potential. To reduce disturbance of the floating gate potential of unselected memory cells during FN erase operations, the unselected word lines are brought to a positive potential rather than ground potential.

Method and apparatus for multiple byte or page mode programming of a flash memory array

A convergence signal includes a series of voltage pulses used to perform a convergence procedure in one or more flash EEPROM memory cells (transistors). In one instance subsequent voltage pulses in the convergence signal each have a higher voltage than the preceding pulse. In another instance, subsequent voltage pulses in the convergence signal each have a longer duration than the preceding pulse. An integrated circuit includes an array of memory cells and an erase control unit which controls the application of the convergence signal to one or more memory cells. The integrated circuit may be either serial or parallel flash EEPROM in which bulk, sector, or page mode erasing is used.

Threshold voltage convergence

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San Jose, CA, United States of America

Dung Tran