Microsemi Corporation

Advanced Power Technology Corporation

Microchip Technology Inc.

Dumitru Sdrulla

Bruce Odekirk

Marc H Vandenberg

Dah W Tsang

Amaury Gendron-Hansen

Douglas A Pike, Jr

James M Katana

Shanqi Zhao

Avinash Srikrishnan Kashyap

Nathaniel C Berliner

Cecil Kent Walters

Theodore O Meyer

Duane Edward Levine

John W Mosier, Ii, Deceased

Martin David Birch

Jinshu Zhang

Feng Zhao

Eric Karlsson

A high-voltage termination for a semiconductor device includes a substrate of a first conductivity type, an implanted device region of a second conductivity type of the semiconductor device, a shallow trench disposed in the substrate adjacent to the implanted device region, a doped extension region of the second conductivity type extending between the implanted device region and a first edge of the shallow trench adjacent to the implanted device region, a junction termination extension region of the second conductivity type formed in the shallow trench contacting the extension region and extending past a second edge of the shallow trench opposite the implanted device region, an insulating layer formed over at least a portion of the extension region and over the junction termination extension region, and a metal layer formed over the insulating layer extending into at least a portion of the shallow trench and electrically connected to the extension region.

Space efficient high-voltage termination and process for fabricating same

A power transistor assembly and method of mitigating short channel effects in a power transistor assembly are provided. The power transistor assembly includes a first layer of semiconductor material formed of a first conductivity type material and a hard mask layer covering at least a portion of the first layer and having a window therethrough exposing a surface of the first layer. The power transistor assembly also includes a first region formed in the first layer of semiconductor material of a second conductivity type material and aligned with the window, one or more source regions formed of first conductivity type material within the first region and separated by a portion of the first region, and an extension of the first region extending laterally through the surface of the first layer.

Method and assembly for mitigating short channel effects in silicon carbide MOSFET devices

A semiconductor device constituted of: a semiconductor layer; and a field layer patterned on said semiconductor layer, said field layer constituted of material having characteristics which block diffusion of mobile ions and maintain structural integrity at activation temperatures of up to 1200 degrees centigrade.

Semiconductor device with improved field layer

A high power, high current Unidirectional Transient Voltage Suppressor, formed on SiC starting material is disclosed. The device is structured to avalanche uniformly across the entire central part (active area) such that very high currents can flow while the device is reversely biased. Forcing the device to avalanche uniformly across designated areas is achieved in different ways but consistently in concept, by creating high electric fields where the device is supposed to avalanche (namely the active area) and by relaxing the electric field across the edge of the structure (namely in the termination), which in all embodiments meets the conditions for an increased reliability under harsh environments.

SiC transient voltage suppressor

A Vertical Multiple Implanted Silicon Carbide Power MOSFET (VMIMOSFET) includes a first conductivity semiconductor substrate, a first conductivity semiconductor drift layer on the top of the substrate, a multitude of second conductivity layers implanted in the drift layer. The body layer is where the channel is formed. A first conductivity source layer is interspaced appropriately inside of the second conductivity layers. A gate oxide of a certain thickness and another oxide of a different thickness, a greater thickness than the gate oxide, placed in between the body layers but in such way that its shape does not distort the gate oxide in the channel. A charge compensated body layer of the second conductivity formed outside of the channel region and only at specific high electric field locations in the structure. The device and the manufacturing method deliver a power SiC MOSFET with increased frequency of operation and reduced switching losses.

Low loss SiC MOSFET

A Vertical Power MOSFET (VDMOS) device with special features that enable the Power MOSFET or IGBT device to withstand harsh radiation environments and the process of making such a device is described. All implanted and diffused layers are 'self aligned' to a 'Sacrificial Poly' layer, which later on is removed, preparing the wafers for a &#x201c;late gate&#x201d; oxide to be grown. A starting material with graded doping profile in the epitaxial layer on the substrate is shown to increase the SEB capability of the Power MOSFET.

Pseudo self aligned radhard MOSFET and process of manufacture

A high voltage power semiconductor device includes high reliability-high voltage junction termination with a charge dissipation layer. An active device area is surrounded by a junction termination structure including one or more regions of a polarity opposite the substrate polarity. A tunneling oxide layer overlays the junction termination area surrounding the active device area in contact with the silicon substrate upper surface. A layer of undoped polysilicon overlays the tunneling oxide layer and spans the junction termination area, with connections to an outer edge of the junction termination structure and to a grounded electrode inside of the active area. The tunneling oxide layer has a thickness that permits hot carriers formed at substrate upper surface to pass through the tunneling oxide layer into the undoped polysilicon layer to be dissipated but sufficient to mitigate stacking faults at the silicon surface.

High reliability-high voltage junction termination with charge dissipation layer

A SiC Power Semiconductor device of the Field Effect Type (MOSFET, IGBT or the like) with 'muted' channel conduction, negative temperature coefficient of channel mobility, in situ 'ballasted' source resistors and optimized thermal management of the cells for increased Safe Operating Area is described. Controlling the location of the Zero Temperature Crossover Point (ZTCP) in relationship to the drain current is achieved by the partition between the &#x201c;active&#x201d; and &#x201c;inactive&#x201d; channels and by adjusting the mobility of the carriers in the channel for the temperature range of interest. The &#x201c;Thermal management&#x201d; is realized by surrounding the &#x201c;active&#x201d; cells/fingers with &#x201c;inactive&#x201d; ones and the &#x201c;negative&#x201d; feedback of the drain/collector current due to local increase of the gate bias is achieved by implementing in-situ &#x201c;ballast&#x201d; resistors inside of each source contact.

SiC power vertical DMOS with increased safe operating area

High voltage semiconductor devices with high-voltage termination structures are constructed on lightly doped substrates. Lightly doped p-type substrates are particularly prone to depletion and inversion from positive charges, degrading the ability of associated termination structures to block high voltages. To improve the efficiency and stability of termination structures, second termination regions of the same dopant type as the substrate, more heavily doped than the substrate but more lightly doped than first termination regions, are positioned adjoining the first termination regions. The second termination regions raise the field threshold voltage where the surface is vulnerable and render the termination structure substantially insensitive to positive charges at the surface. The use of higher dopant concentration in the gap region without causing premature avalanche is facilitated by only creating second termination regions for regions lacking field plate protection.

Edge termination for high voltage semiconductor device

A merged PN/Schottky diode is provided having a substrate of a first conductivity type and a grid of doped wells of the second conductivity type embedded in the substrate. A Schottky barrier metal layer makes a Schottky barrier contact with the surface of the substrate above the grid. Selected embedded wells in the grid make a Schottky barrier contact to the Schottky barrier metal layer, while most embedded wells do not. The diode forward voltage drop is reduced for the same diode area with reverse blocking benefits similar to a conventional JBS structure.

Schottky barrier diode (SBD) and its off-shoot merged PN/Schottky diode or junction barrier Schottky (JBS) diode

An improved Fast Recovery Diode comprises a main PN junction defining a central conduction region for conducting high current in a forward direction and a peripheral field spreading region surrounding the central conduction region for blocking high voltage in the reverse direction. The main PN junction has an avalanche voltage equal to or lower than an avalanche voltage of the peripheral field spreading region so substantially the entire said main PN junction participates in avalanche conduction. This rugged FRED structure can also be formed in MOSFETS, IGBTS and the like.

Design and fabrication of rugged FRED, power MOSFET or IGBT

Design and fabrication of rugged FRED

A gate power MOSFET on substrate (20) has a P-body layer (26), N-drain layer (24) and optional P+ layer (22) for IGBT. Layer (430) on surface (28) patterns areas (446) as stripes or a matrix, and protected areas. Undercut sidewalls (444) of thickness (452), with protruding rims (447), contact the sides of layer (434'). Trench (450) in areas (446) has silicon sidewalls aligned to oxide sidewall (447) and extending depthwise through P-body layer (26) to depth (456). Gate oxide (460) is formed on the trench walls and gate polysilicon (462) refills trench (450) to a level (464) near surface (28) demarcated by the undercut sidewall rims (447). Oxide (468) between spacers (444) covers polysilicon (462). Removing layer (430) exposes surface (28') between the sidewalls (444). Source layer (72) is doped atop the body layer (26') and then trenched to form trench (80) having sidewalls aligned to inner side faces of sidewalls (444). Trench (80) defines vertically-oriented source and body layers (86, 90) stacked along oxide layer (460) to form vertical channels on opposite sides of trench (80). Layers (86, 90) have a lateral thickness (88) of the undercut sidewalls (444) and rims (447) spacers. Conductor (94) contacts the N-source and P-body layers, and enhanced P+ region in trench (80).

High density power device fabrication process using undercut oxide

For IGBT, MCT or like devices, the substrate is formed with P+, N+ and N- layers and PN diffusions to define body and source regions in the N-layer and a MOS-gated channel at the upper surface. The N-layer is sized and doped (.about.10.sup.14 /cm.sup.3) to block reverse bias voltage. The N+ layer is &gt;20 .mu.m thick and doped below .about.10.sup.17 /cm.sup.3 but above the N- doping to enhance output impedance and reduce gain at high V.sub.ce conditions. Or the N+ layer is formed with a thin (.about.5 .mu.m) highly doped (&gt;10.sup.17 /cm.sup.3) layer and a thick (&gt;20 .mu.m) layer of .about.10.sup.16 /cm.sup.3 doping. A platinum dose of 10.sup.13 to 10.sup.16 /cm.sup.3 is ion implanted and diffused into the silicon to effect lifetime control. Gate and source contacts and body and source diffusions have an inter-digitated finger pattern with complementary tapers to minimize current crowding and wide gate buses to minimize signal delay. P+ doping beneath and marginally surrounding the gate pads and main gate bus negates breakdown conditions in widely spaced body regions and convex localities at the source finger end. Wide secondary gate buses parallel to the gate fingers have a P+ doped central stripe and transverse shorting bars spaced along their length. A non-polarizable PECVD passivation film of low phosphorus PSG and nitride or oxynitride or of oxynitride alone is made by controlling ionized gas residence time, silane partial pressure, and oxygen ratio during deposition, to minimize incorporation of Si--H into the film.

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Bend, OR, United States of America

Dumitru Sdrulla