Texas Instruments Corporation

Photodigm Inc.

Duane E Carter

Cecil J Davis

Rhett B Jucha

Jiong-Ping Lu

Ming J Hwang

James D Huffman

Wei-Yung Hsu

Sue E Crank

Brian L Ray

Richard Lee Knipe

Qi-Zhong Hong

Antonio L P Rotondaro

William R McKee

Donald L Plumton

Lionel S White, Jr

Gary Alan Evans

Rodney Dean Miller

John E Spencer

Gabriel George Barna

Austin L Huang

John I Jones

Frank C Sulzbach

Henry W Trombley

Jay Bernard Kirk

Gishi Chung

Robert E Meier

Stephen W Russell

James G Frank

Fred D Fishburn

Jeff D Achenbach

Darren S Lee

David Alan Willis

Richard P VanMeurs

Dave Autery

Timothy J Wooldridge

Yung Liu

G Sreenivas

Dick N Anderson

Zuhair Hilali

Duy Phan

A uniform coating is provided using surface features. Multiple ridges or other shapes are fabricated near an area of interest to allow for uniform coating in between the ridges. Areas at either ends of the ridges are left open to allow for excess pooling of photoresist liquid and to aid in obtaining uniform coating. The photoresist liquid or other coating fluid is applied to the sample and spun dry. A soft-bake process is performed to evaporate remaining solvents. An element, such as a diffractive, refractive, or reflective grating structure, is then formed in the area of interest using the uniform photoresist coating.

Coating thickness control using surface features

A method of isolating an exposed conductive surface. An aluminum layer ( ) is selectively formed over the exposed conductive ( ) surface (e.g., Cu) but not over the surrounding dielectric ( ) surface using a thermal CVD process. The aluminum layer ( ) is then oxidized to form a thin isolating aluminum-oxide ( ) over only the conductive surface. The isolating aluminum-oxide provides a barrier for the Cu while taking up minimal space and reducing the effective dielectric constant.

Process for isolating an exposed conducting surface

Contacts for an electronic device are formed by providing a substrate ( ) that has at least two access line structures ( ) for a memory array ( ) and a periphery structure ( ) for a peripheral circuit ( ) to the memory array ( ). A first insulative layer ( ) is formed outwardly of the substrate ( ), the access line structures ( ), and the periphery structure ( ). A contact area of the periphery structure ( ) is exposed through the first insulative layer ( ) while maintaining the first insulative layer ( ) over at least a contact overlap portion ( ) of the access line structures ( ). A second insulative layer ( ) is formed outwardly of the substrate ( ), the access line structures ( ), the periphery structure ( ), and the first insulative layer ( ). A self-aligned contact hole ( ) overlapping the contact overlap portion ( ) of the access line structures ( ) and a periphery contact hole ( ) overlapping the contact area ( ) of the periphery structure ( ) are formed through the second insulative layer ( ) with a same mask ( ). A self-aligned contact ( ) is formed in the self-aligned contact hole ( ) and a periphery contact ( ) is formed in the periphery contact hole ( ).

Method for forming memory array and periphery contacts using a same mask

A spatial light modulator with an anti-reflective coating (ARC),integrated into its structure. The manufacturing of the device is altered to include deposition of an ARC,and any necessary patterning and etching to allow the elements of the array to operate properly. The ARC could reside in several places of the element structure including over the addressing circuitry,over a middle layer,or on the underside of the reflective structure,Micromechanical spatial light modulators, as well as non-moving modulators, such as reflective and transmissive LCD modulators can use the invention.

Anti-reflective coatings for spatial light modulators

A dry etch using CFx in an O2-rich environment will clean the contact/via at the same time it retracts a layer of TiN enclosed in the dielectric layer, such as the plate layer in a Capacitor-Under-Bitline DRAM cell.

Simplifying conductive plate/via isolation

A method for fabricating a low resistivity polymetal silicide conductor/gate comprising, the steps of forming a polysilicon (,) over a gate oxide (,) followed by protection of the polysilicon (,) with a sacrificial material (,), is disclosed. Gate sidewalls (,) are created to protect the sides of the polysilicon (,) and the sacrificial material (,), followed by stripped the sacrificial material (,) to expose the top surface of the polysilicon (,). Next, a diffusion barrier (,) is deposited over the exposed polysilicon (,) and a metal layer (,) is selectively grown on the diffusion barrier (,) to form a gate contact and conductor. Finally, a dielectric layer (,) is deposited over the selectively grown metal layer (,), the sidewalls (,) and the gate oxide (,).

Low resistivity poly-silicon gate produced by selective metal growth

A metal-poly stack gate structure and associated method for forming a conductive barrier layer between W and poly in the metal-gate stack gate structure. The process includes the steps of depositing doped silicon on a substrate; forming nitride on the deposited silicon; depositing a metal on the nitride to form a metal/nitride/deposited silicon stack; and thermally treating the stack to transform the nitride into a conductive barrier layer between the metal and the deposited silicon. The thermal treatment transforms the nitride layer (SiN.sub.x or SiN.sub.x O.sub.y) into a conductive barrier (WSi.sub.x N.sub.y or WSi.sub.x N.sub.y O.sub.z) to form a W/barrier/poly stack gate structure. The barrier layer blocks reaction between W and Si, enhances sheet resistance, enhances adhesion between the W and the poly, and is stable at high temperatures.

Stable and low resistance metal/barrier/silicon stack structure and

A micromirror array fabricated on a semiconductor substrate 708. The micromirrors in the micromirror array logically divided into an interior active region 704 which selectively modulates light striking the mirrors in the interior active region 704, and an exterior border region 702 for producing a dark border around the image produced by the interior active region 704. A gap between each mirror allows adjacent mirrors to rotate. The gap 712 between mirrors in the interior active region 704 of the array is larger than the gap 710 between at least some of the mirrors in the exterior border region 702. The smaller gap 710 in the exterior region 702 is enabled by restricting mirrors in the exterior region 702 to a single direction of rotation.

Reduced micromirror mirror gaps for improved contrast ratio

A method of operating a micromechanical device. The device is in a first state. Data for the next state of the device is loaded onto the activation circuitry of the device, where the next state may be the same state the device is currently in, or a state different from the first state. The equilibrium of the device is shifted away from the next state, by making the data appear complementary to the true data for the next state. When the trapping field is removed or lowered, and a signal to start the transition is provided, the device moves to its new state and the trapping field is reapplied. The data can be made to look complementary by either loading the complements to the true data, or by reversing the polarity of the trapping field.

Complemetary reset scheme for micromechanical devices

An etching apparatus (10) includes a process chamber (12) partially surrounded by an upper electrode (14) and a lower electrode (16). A semiconductor material (18) lies within the process chamber (12) and in contact with the lower electrode (16). The lower electrode (16) is connected to a first power supply (22) operating at a substantially high frequency and is also connected to a second power supply (24) operating at a relatively low frequency. The lower frequency of the second power supply (24) provides a degree of anisotropic control to the trench etching process performed on the semiconductor material (18). The added anisotropic control allows for the elimination of sidewall deposition enhancing materials within a plasma chemistry introduced into the process chamber (12) by a gas distributor (20). Without the requirement of a sidewall deposition enhancing material during trench etching of the semiconductor material (18), buildup of residue due to sidewall deposition does not occur within process chamber (12).

Method and apparatus of etching a clean trench in a semiconductor

A method is disclosed for preventing formation of undesirable polysilicon word line gate filaments in integrated circuit devices such as VLSI dynamic random access memories employing field plate isolation. Before the word lines are processed, an oxide layer is formed in the field plate openings beneath sidewalls of nitride along the edges of the field plate openings. The oxide layer partially fills an undercut area beneath a dip out of the sidewall of nitride. The dip out of the sidewall of nitride is removed. The removal of the dip out and the partial filling of the undercut area reduces the possibility of polysilicon word line filaments from forming around the edge of the field plate openings in the undercut area when the word lines are later added. A field plate isolated memory device is also disclosed wherein along the edges of the field plate openings, the partially filling oxide layer and the sidewall nitride layer are approximately coincident.

Method to eliminate gate filaments on field plate isolated devices

A method for etching a tungsten film which includes introducing activated species of a halogenated hydrocarbon to the tungsten film.

Method for etching tungsten

A void (60) is created in a semiconductor substrate (52) by forming a cavity which is subsequently filled with an organic polymer (66). The organic polymer is masked and etched to form a spacer. A dielectric (70) fills the portions of the cavity where the organic polymer was etched away. The organic polymer is subsequently etched leaving a void.

Organic space holder for trench processing

A thin film etching process, wherein the rate of deposition of a robust sidewall passivant is controlled so that passivants can be continually deposited on the sidewalls of the resist pattern to change the geometry of the resist pattern during the processing step. That is, the existing pattern is modified as if a sidewall filament has been deposited on it, which can be advantageous for many purposes, without the added process complexity required by a sidewall filament process.

Selective etching of tungsten by remote and in situ plasma generation

An apparatus for reactive ion etching or plasma etching wherein the wafer faces downward. The process gas is supplied through a distributor which is below the wafer and has orifices pointing away from the wafer. The vacuum (exhaust) port is below the distributor, so that there is no bulk gas flow near the face of the wafer. Preferably transport of the process gasses and their products to the face of the wafer is dominated by diffusion.

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Plano, TX, United States of America

Duane E Carter