Intel Corporation

Drew W Delaney

Ravi Kiran Nalla

John Stephen Guzek

Javier Soto Gonzalez

Pramod Malatkar

Hamid Azimi

Johanna M Swan

Kemal Aygun

Digvijay Ashokkumar Raorane

Daniel N Sobieski

Mohit Mamodia

Edward A Zarbock

Suresh V Pothukuchi

Rahul N Manepalli

Mathew J Manusharow

Dilan Seneviratne

Saeed S Shojaie

Mahesh Sambasivam

Javier Solo Gonzalez

Ravi K Nailla

An apparatus including a die including a device side with contact points and lateral sidewalls defining a thickness of the die; a build-up carrier coupled to the die, the build-up carrier including a plurality of alternating layers of patterned conductive material and insulating material, wherein at least one of the layers of patterned conductive material is coupled to one of the contact points of the die; and an interference shield including a conductive material disposed on the die and a portion of the build-up carrier. The apparatus may be connected to a printed circuit board. A method including forming a build-up carrier adjacent a device side of a die including a plurality of alternating layers of patterned conductive material and insulating material; and forming a interference shield on a portion of the build-up carrier.

Method of forming an interference shield on a substrate

The present disclosure relates to the field of fabricating microelectronic packages and the fabrication thereof, wherein a microelectronic device may be formed within a bumpless build-up layer coreless (BBUL-C) microelectronic package and wherein a warpage control structure may be disposed on a back surface of the microelectronic device. The warpage control structure may be a layered structure comprising at least one layer of high coefficient of thermal expansion material, including but not limited to a filled epoxy material, and at least one high elastic modulus material layer, such as a metal layer.

Bumpless build-up layer package warpage reduction

An apparatus includes a coreless substrate with a through-silicon via (TSV) embedded die that is integral to the coreless substrate. The apparatus includes a subsequent die that is coupled to the TSV die and that is disposed above the coreless substrate.

Die-stacking using through-silicon vias on bumpless build-up layer substrates including embedded-dice, and processes of forming same

Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods may include attaching a die to a carrier material, wherein the carrier material comprises a top layer and a bottom layer separated by an etch stop layer; forming a dielectric material adjacent the die, forming a coreless substrate by building up layers on the dielectric material, and then removing the top layer carrier material and etch stop layer from the bottom layer carrier material.

Forming functionalized carrier structures with coreless packages

Thin film based electromagnetic interference shielding with BBUL/coreless packages

A microelectronic package comprises a die () and a plurality of electrically conductive layers () and electrically insulating layers (), including a first electrically insulating layer () closer to the die than any other electrically insulating layer) and second () and third electrically insulating layers (). Each electrically insulating layer has a corresponding glass transition temperature, coefficient of thermal expansion, and modulus of elasticity. The modulus of elasticity of the second electrically insulating layer is greater than that for the first electrically insulating layer, while CTEfor the second electrically insulating layer is greater than CTEfor the first. CTEfor the third electrically insulating layer is less than CTEfor the first electrically insulating layer. In an embodiment an electrically insulating layer is a glass cloth layer () that is an outermost layer of the microelectronic package.

Microelectronic package and stacked microelectronic assembly and computing system containing same

A microelectronic package includes a substrate (), a die () embedded within the substrate, the die having a front side () and a back side () and a through-silicon-via () therein, build-up layers () built up over the front side of the die, and a power plane () in physical contact with the back side of the die. In another embodiment, the microelectronic package comprises a substrate (), a first die () and a second die () embedded in the substrate and having a front side () and a back side () and a through-silicon-via () therein, build-up layers () over the front sides of the first and second dies, and an electrically conductive structure () in physical contact with the back sides of the first and second dies.

Microelectronic package and method of manufacturing same

Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods may include forming a cavity in a carrier material, attaching a die in the cavity, wherein a backside of the die comprises a metal filled DBF, forming a dielectric material adjacent the die and on a bottom side of the carrier material, forming a coreless substrate by building up layers on the dielectric material, and removing the carrier material from the coreless substrate.

Forming metal filled die back-side film for electromagnetic interference shielding with coreless packages

Methods of forming microelectronic devices by disposing a radiation curable underfill material or adhesive material between a substrate and a microelectronic die, and exposing any radiation curable material which bleeds-out therefrom to radiation before or immediately after disposition, thereby reducing the extent of material bleed-out.

Growing community of inventors

Chandler, AZ, United States of America

Drew W Delaney