Freescale Semiconductor,inc.

Nxp USA, Inc.

Dragan Zupac

Moaniss Zitouni

Ganming Qin

Pon Sung Ku

Michael F Petras

Edouard D De Fresart

Sandra J Wipf

Theresa M Keller

Evgueniy Nikolov Stefanov

Edouard De Frésart

Brian D Griesbach

Evan F Yu

Joel M Keys

Elizabeth C Glass

Edouard D De Frèsart

A recess is formed at a semiconductor layer of a device to define a plurality of mesas. An active trench portion of the recess residing between adjacent mesas. A termination portion of the trench residing between the end of each mesa and a perimeter of the recess. The transverse spacing between the mesas and the lateral spacing between the mesas and an outer perimeter of a recess forming the mesas are substantially the same. A shield structure within the trench extends from the region between the mesas to the region between the ends of the mesas and the outer perimeter of the recess forming the mesas. A contact resides between a shield electrode terminal and the shield portion residing in the trench.

Trench MOSFET shield poly contact

A device includes a semiconductor substrate having a surface, a trench in the semiconductor substrate extending vertically from the surface, a body region laterally adjacent the trench, spaced from the surface, having a first conductivity type, and in which a channel is formed during operation, a drift region between the body region and the surface, and having a second conductivity type, a gate structure disposed in the trench alongside the body region, recessed from the surface, and configured to receive a control voltage is applied to control formation of the channel, and a gate dielectric layer disposed along a sidewall of the trench between the gate structure and the body region. The gate structure and the gate dielectric layer have a substantial vertical overlap with the drift region such that electric field magnitudes in the drift region are reduced through application of the control voltage.

Bidirectional trench FET with gate-based resurf

A semiconductor device includes a substrate and a semiconductor layer having a first conductivity type. The semiconductor device further includes first and second trenches extending into the semiconductor layer from a surface of the semiconductor layer, each of the first and second trenches including a corresponding gate electrode. The semiconductor device further includes a body region having a second conductivity type different than the first conductivity type and a source contact region having the first conductivity type. The body region is disposed in the semiconductor layer below the surface of the semiconductor layer and between a sidewall of the first trench and an adjacent sidewall of a second trench. The source contact region is disposed in the semiconductor layer between the body region and the surface of the semiconductor layer and extending between the sidewall of the first trench and the corresponding sidewall of the second trench.

Trench gate FET with self-aligned source contact

A bidirectional trench FET device includes a semiconductor substrate, a trench in the substrate extending vertically from the surface of the substrate, and a body region laterally adjacent the trench. A source region is disposed in the semiconductor substrate between the body region and the surface of the substrate. A dielectric layer is disposed over the surface and a body electrode is disposed over the dielectric layer. A body contact plug extends through the dielectric layer to interconnect the body region with the body electrode, and the body contact plug is electrically isolated from the source region. Two separate metal layers are implemented to make multiple body and source contacts electrically isolated from one another throughout the active area of the device. The low resistive path by the body contact plug and the separate metal layers enables suppression of bipolar snapback without losing bidirectional switching capability.

Bidirectional MOSFET with suppressed bipolar snapback and method of manufacture

A semiconductor amplifier is provided comprising, a substrate and one or more unit amplifying cells (UACs) formed on the substrate, wherein each UAC is laterally surrounded by a first lateral dielectric filled trench (DFT) isolation wall extending at least to the substrate and multiple UACs are surrounded by a second lateral DFT isolation wall of similar depth outside the first isolation walls, and further semiconductor regions lying between the first isolation walls when two or more unit cells are present, and/or lying between the first and second isolation walls, are electrically floating with respect to the substrate. This reduces the parasitic capacitance of the amplifying cells and improves the power added efficiency. Excessive leakage between buried layer contacts when using high resistivity substrates is avoided by providing a further semiconductor layer of intermediate doping between the substrate and the buried layer contacts.

High efficiency amplifier with reduced parasitic capacitance

A power transistor () comprises a plurality of unit cell devices (), a base contact configuration, an emitter contact configuration, and a collector contact configuration. The plurality of unit cell devices is arranged along an axis (), each unit cell device including base (), emitter (), and collector () portions. The base contact configuration includes (i) a first base feed () coupled to the base portion of each unit cell device via a first end of at least one base finger () associated with a corresponding unit cell device and (ii) a second base feed () coupled to the base portion of each unit cell device via an opposite end of the at least one base finger associated with the corresponding unit cell device. The emitter contact configuration includes (i) a first emitter feed () coupled to the emitter portion of each unit cell device via a first end of an emitter metallization () associated with a corresponding unit cell device and (ii) a second emitter feed () coupled to the emitter portion of each unit cell device via an opposite end of the emitter metallization associated with the corresponding unit cell device. The collector contact configuration includes a collector feed () coupled to the collector portion of each unit cell device.

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Chandler, AZ, United States of America

Dragan Zupac