Applied Materials, Inc.

Lam Research Corporation

Other

International Business Machines Corporation

Siemens Aktiengesellschaft

Lam Research Group

Dragan Valentin Podlesnik

Anisul Haque Khan

Ajay Kumar

Jeffrey D Chinn

Wei Liu

Shaoher X Pan

David S Mui

Ji Zhu

David S L Mui

Arjun Mendiratta

Satish Srinivasan

Shih-Chung Kon

Yiqiong Wang

Grant Peng

Gene S Lee

Sharma V Pamarthy

Jeff Chinn

Nam-Hun Kim

Maocheng Li

Yizhak Sabba

Yan Ye

John C Forster

Thorsten B Lill

Peter K Loewenhardt

Arthur H Sato

Meihua Shen

Katrina Mikhaylichenko

Mark Henry Wilcoxson

Padmapani Nallan

Mark Naoshi Kawaguchi

Shashank C Deshmukh

Xue-Yu Qian

Vijayakumar C Venugopal

Stephan Wege

Donna Rizzone Cote

Valentin N Todorov

Seokmin Yun

Anthony J Konecni

Virinder Grewal

Sanjay M Thekdi

Songlin Xu

Chung Ho Huang

Xueyu Qian

Alok Jain

Virinder S Grewal

Zhiwen Sun

Jeffrey D Chin

Yoshi Tanase

Connie Lam

Axel Henke

Kenju Nishikido

Michelle Siew Mooi Low

Gang Zou

A process-level troubleshooting architecture (PLTA) configured to facilitate substrate processing in a plasma processing system is provided. The architecture includes a process module controller. The architecture also includes a plurality of sensors, wherein each sensor of the plurality of sensors communicates with the process module controller to collect sensed data about one or more process parameters. The architecture further includes a process-module-level analysis server, wherein the process-module-level analysis server communicates directly with the plurality of sensors and the process module controller. The process-module-level analysis server is configured for receiving data, wherein the data include at least one of the sensed data from the plurality of sensors and process module and chamber data from the process module controller. The process-module-level analysis server is also configured for analyzing the data and sending interdiction data directly to the process module controller when a problem is identified during the substrate processing.

Arrangement for identifying uncontrolled events at the process module level and methods thereof

Apparatus and methods for removing particle contaminants from a surface of a substrate includes coating a layer of a viscoelastic material on the surface. The viscoelastic material is coated as a thin film and exhibits substantial liquid-like characteristic. An external force is applied to a first area of the surface coated with the viscoelastic material such that a second area of the surface coated with the viscoelastic material is not substantially subjected to the applied force. The force is applied for a time duration that is shorter than a intrinsic time of the viscoelastic material so as to access solid-like characteristic of the viscoelastic material. The viscoelastic material exhibiting solid-like characteristic interacts at least partially with at least some of the particle contaminants present on the surface. The viscoelastic material along with at least some of the particle contaminants is removed from the first area of the surface while the viscoelastic material is exhibiting solid-like characteristics.

Method of particle contaminant removal

A system and method for removing polymer residue from around a metal gate structure formed on a surface of a substrate during a post-etch cleaning operation includes determining a plurality of process parameters associated with the metal gate structure and the polymer residue to be removed. A plurality of fabrication layers define the metal gate structure and the process parameters define characteristics of the fabrication layers and the polymer residue. A first cleaning chemistry and second cleaning chemistry are identified and a plurality of application parameters associated with the first and second cleaning chemistries are defined based on the process parameters. The first and second application chemistries are applied sequentially in a controlled manner using the application parameters to substantial remove the polymer residue while preserving the structural integrity of the gate structure.

Method and apparatus for surface treatment of semiconductor substrates using sequential chemical applications

The embodiments of the present invention provide methods for cleaning patterned substrates with fine features. The methods for cleaning patterned substrate have advantages in cleaning patterned substrates with fine features without substantially damaging the features by using the cleaning materials described. The cleaning materials are fluid, either in liquid phase, or in liquid/gas phase, and deform around device features; therefore, the cleaning materials do not substantially damage the device features or reduce damage all together. The cleaning materials containing polymers of a polymeric compound with large molecular weight capture the contaminants on the substrate. In addition, the cleaning materials entrap the contaminants and do not return the contaminants to the substrate surface. The polymers of one or more polymeric compounds with large molecular weight form long polymer chains, which can also be cross-linked to form a network (or polymeric network). The long polymer chains and/or polymer network show superior capabilities of capturing and entrapping contaminants, in comparison to conventional cleaning materials.

Methods for particle removal by single-phase and two-phase media

The embodiments of the present invention provide improved materials for cleaning patterned substrates with fine features. The cleaning materials have advantages in cleaning patterned substrates with fine features without substantially damaging the features. The cleaning materials are fluid, either in liquid phase, or in liquid/gas phase, and deform around device features; therefore, the cleaning materials do not substantially damage the device features or reduce damage all together. The cleaning materials containing polymers of a polymeric compound with large molecular weight capture the contaminants on the substrate. In addition, the cleaning materials entrap the contaminants and do not return the contaminants to the substrate surface. The polymers of one or more polymeric compounds with large molecular weight form long polymer chains, which can also be cross-linked to form a network (or polymeric network). The long polymer chains and/or polymer network show superior capabilities of capturing and entrapping contaminants, in comparison to conventional cleaning materials.

Materials for particle removal by single-phase and two-phase media

The embodiments of the present invention provide apparatus for cleaning patterned substrates with fine features with cleaning materials. The apparatus using the cleaning materials has advantages in cleaning patterned substrates with fine features without substantially damaging the features. The cleaning materials are fluid, either in liquid phase, or in liquid/gas phase, and deform around device features; therefore, the cleaning materials do not substantially damage the device features or reduce damage all together. The cleaning materials containing polymers of a polymeric compound with large molecular weight capture the contaminants on the substrate. In addition, the cleaning materials entrap the contaminants and do not return the contaminants to the substrate surface. The polymers of one or more polymeric compounds with large molecular weight form long polymer chains, which can also be cross-linked to form a network (or polymeric network). The long polymer chains and/or polymer network show superior capabilities of capturing and entrapping contaminants, in comparison to conventional cleaning materials.

Apparatus for particle removal by single-phase and two-phase media

A method for operating a plasma reactor to etch high-aspect-ratio features on a workpiece in a vacuum chamber. The method comprises the performance of an etch process followed by a flash process. During the etch process, a first gas is supplied into the vacuum chamber, and a plasma of the first gas is maintained for a first period of time. The plasma of the first gas comprises etchant and passivant species. During the flash process, a second gas comprising a deposit removal gas is supplied into the vacuum chamber, and a plasma of the second gas is maintained for a second period of time. The DC voltage between the workpiece and the plasma of the second gas during the second period of time is significantly less than the DC voltage between the workpiece and the plasma of the first gas during the first period of time.

Method for etching high-aspect-ratio features

The present disclosure pertains to our discovery of a particularly efficient method for etching a multi-part cavity in a substrate. The method provides for first etching a shaped opening, depositing a protective layer over at least a portion of the inner surface of the shaped opening, and then etching a shaped cavity directly beneath and in continuous communication with the shaped opening. The protective layer protects the etch profile of the shaped opening during etching of the shaped cavity, so that the shaped opening and the shaped cavity can be etched to have different shapes, if desired. In particular embodiments of the method of the invention, lateral etch barrier layers and/or implanted etch stops are also used to direct the etching process. The method of the invention can be applied to any application where it is necessary or desirable to provide a shaped opening and an underlying shaped cavity having varying shapes. The method is also useful whenever it is necessary to maintain tight control over the dimensions of the shaped opening.

Method of micromachining a multi-part cavity

A method and apparatus for reducing the sensitivity of semiconductor processing to chamber conditions is provided. Process repeatability of common processes are affected by changing surface conditions which alter the recombination rates of processing chemicals to the chamber surfaces. In one aspect of the invention, a composition of one or more etchants is selected to optimize the etch performance and reduce deposition on chamber surfaces. The one or more etchants are selected to minimize buildup on the chamber surfaces, thereby controlling the chamber surface condition to minimize changes in etch rates due to differing recombination rates of free radicals with different surface conditions and achieve etch repeatability. In another embodiment, the etchant chemistry is adjusted to reduce the change to internal surface conditions after a cleaning cycle. In another embodiment, a process recipe is selected to reduce the sensitivity of the etch process to the chamber conditions. In another embodiment, chamber surface materials are selected to minimize the differences in recombination rates of free radicals on the surface materials and the byproduct depositions formed on the materials during processing.

Methodologies to reduce process sensitivity to the chamber condition

This invention is directed to a method for etching films on semiconductor substrates and cleaning etch chambers. The method includes an improved processing sequence and cleaning method where residue formed from processing a previous substrate are cleaned by the etching process used to remove an exposed layer of material from the present substrate. The process provides improved substrate throughput by combining the step to clean residue from a previous substrate with an etch step conducted on the present substrate. Applicants have found the method particularly useful in processing structures such as DRAM stacks, especially where the residue is formed by a trench etched in the previous silicon substrate and the exposed layer etched from the present substrate is silicon nitride.

Apparatus for performing self cleaning method of forming deep trenches in silicon substrates

A method of etching high aspect ratio, anisotropic deep trench openings in a silicon substrate coated with a multilayer mask comprising in sequence a pad oxide layer, a silicon nitride layer, a doped or undoped silicon oxide hard mask layer, a polysilicon hard mask layer, an antireflection coating and a patterned photoresist layer in a single chamber comprising patterning the antireflection coating and hard mask layer, removing the photoresist and antireflection layers with oxygen, using the patterned polysilicon as a hard mask layer etching an opening in the silicon oxide hard mask layer, the silicon nitride layer and the pad oxide layer, removing the polysilicon hard mask layer with CF4/CHF3, and etching an anisotropic deep trench in the silicon substrate using the patterned silicon oxide hard mask layer as a mask and an etchant mixture including nitrogen trifluoride that self-cleans the chamber.

Process for in-situ etching a hardmask stack

Processes for forming trenches within silicon substrates are described. According to an embodiment of the invention, a masked substrate is initially provided that comprises (a) a silicon substrate and (b) a patterned resist layer over the silicon substrate. The patterned resist layer has one or more apertures formed therein. Subsequently, a trench is formed in the substrate through the apertures in the resist layer by an inductive plasma-etching step, which is conducted using plasma source gases that comprise SF , at least one fluorocarbon gas, and N . If desired, Cl can also be provided in addition to the above source gases. The process of the present invention produces chamber deposits in low amounts, while providing high etching rates, high silicon:resist selectivities, and good trench sidewall profile control.

High resist-selectivity etch for silicon trench etch applications

A method and apparatus for dicing a semiconductor wafer using a plasma etch process. The method begins by applying a patterned mask to the integrated circuits on a wafer. The pattern covers the circuits and exposes the streets between the dice. Next, the method deposits a uniform layer of adhesive material upon a carrier wafer. The wafer to be diced is affixed to the carrier wafer via the adhesive material that is sandwiched between the bottom surface of the wafer to be diced and the top surface of the carrier wafer. The combination assembly of the carrier wafer, adhesive and wafer to be diced is placed in an etch reactor that is capable of etching silicon. When the reactive gas is applied to the combination assembly, the etch plasma will consume the unprotected silicon within the streets and dice the wafer into individual integrated circuit chips. The carrier wafer is then removed from the etch chamber with the dice still attached to the adhesive layer. A well-known process is used to remove the adhesive material as well as any mask material and detach the dice from the carrier wafer.

Method for dicing a semiconductor wafer

A process for etching a pattern-masked conductor substrate anisotropically so as to obtain very high etch rates comprising adding a polymer-forming fluorocarbon gas and an etch gas at high flow rates to an etch chamber at etching pressures of 77 millitorr to 100 Torr using a high source power and bias power to the substrate support electrode to form a high density plasma. The gases can be added together, sequentially or alternately.

Process for etching conductors at high etch rates

A method of etching silicon using a plasma generated from a gas comprising fluorine (F), oxygen (O), hydrogen (H) and carbon (C).

Plasma etching of silicon using fluorinated gas mixtures

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Palo Alto, CA, United States of America

Dragan Valentin Podlesnik