International Business Machines Corporation

Globalfoundries Inc.

Douglas Oliver Powell

Voya Rista Markovich

David John Russell

Frank Daniel Egitto

Donald Seton Farquhar

David L Questad

Sri Muthuthamby Sri-Jayantha

Karan Kacker

David Brian Stone

Mark David Poliks

John M Lauffer

Shidong Li

Janak G Patel

Thomas R Miller

Anson Jay Call

Mark C Lamorey

Peter Slota, Jr

Kenneth Michael Fallon

Charles F Carey

Manh-Quan Tam Nguyen

Richard Stuart Zarr

Gary Paul Vlasak

Wolfgang Sauter

Paul Alfred Lauro

Konstantinos I Papathomas

George Frederick Walker

Robert Maynard Japp

Jerome J Cuomo

Sung Kwon Kang

Vijayeshwar Das Khanna

Bruce John Chamberlin

Richard Stephen Graf

Anilkumar Chinuprasad Bhatt

David Noel Light

Roy H Magnuson

Edmund D Blackshear

Anthony P Ingraham

John J Ritsko

Brian Eugene Curcio

Thomas P Gall

James W Fuller, Jr

Jaynal Abedin Molla

Perminder S Bindra

Paul Marian Harvey

Yaping Zhou

David Justin West

Jungihl Kim

James R Stack

George J Saxenmeyer, Jr

Jack A Varcoe

Ekkehard F Miersch

Donald O Anstrom

Joseph P Resavy

William Louis Brodsky

Roger Donell Weekly

Steven Paul Ostrander

Mark C H Lamorey

Jean Audet

James Robert Wilcox

David L Thomas

Amit Kumar Sarkhel

Paul Robert Walling

Kim Joseph Blackwell

Kevin Taylor Knadle

Erwin B Cohen

Marek Andrzej Orlowski

Karan C/0 Ibm United Kingdom Limited Intellectual Property Law Kacker

A laminate structure includes a conductive layer and a dielectric layer in contact with the conductive layer, the dielectric layer comprises a selectively patterned high-modulus dielectric material that balances a differential stress between the conductive layer and the dielectric layer to mechanically stiffen the laminate structure and reduce warpage.

Reduced-warpage laminate structure

An approach is provided in which a laminate substrate includes top layers, bottom layers, and a core layer. The top layers are positioned between the core layer and a top surface metallurgy (TSM) layer and include at least one top conductive layer. The bottom layers are positioned between the core layer and a bottom surface metallurgy (BSM) layer and include at least one bottom conductive layer includes a material void pattern that is based upon the top conductive layer and reduces warpage of the laminate substrate.

Copper feature design for warpage control of substrates

Mechanisms are provided for sacrificial carrier dicing of semiconductor wafers. A bottom layer of a semiconductor wafer is bonded to a top layer of a sacrificial carrier. The semiconductor wafer is diced into a set of chips, such that the dicing cuts through the semiconductor wafer and into the sacrificial carrier and such that the sacrificial carrier dresses a diamond blade of a saw so as to expose one or more new, sharp layers of diamonds on the diamond blade.

Sacrificial carrier dicing of semiconductor wafers

An approach is provided in which a laminate substrate includes top layers, bottom layers, and a core layer. The top layers are positioned between the core layer and a top surface metallurgy (TSM) layer and include at least one top conductive layer. The bottom layers are positioned between the core layer and a bottom surface metallurgy (BSM) layer and include at least one bottom conductive layer that includes a material void pattern that is based upon the top conductive layer and reduces warpage of the laminate substrate.

A stacked via structure for reducing vertical stiffness includes: a plurality of stacked vias, each via disposed on a disc-like structure. The disc-like structure includes a platted through hole landing supporting the plurality of stacked vias. The platted through hole landing includes an etched pattern.

Construction of reliable stacked via in electronic substrates&#x2014;vertical stiffness control method

A stacked via structure for reducing vertical stiffness includes: a plurality of stacked vias, each via disposed on a disc-like structure. The disc-like structure includes a platted through hole landing with a thickness of substantially 3 &#x3bc;m. The platted through hole landing includes an etched pattern and a copper top surface.

A device and/or apparatus having plated through holes (PTHs) which are coated to reduce impedance discontinuity in electronic packages. PTH vias are imbedded in the core of a printed circuit board comprising a core layer, a plurality of buildup layers, a plurality of micro-vias, and a plurality of traces. Traces electrically interconnect each of the micro-vias to PTH vias, forming an electrically conductive path. PTHs are coated with a magnetic metal material, such as nickel, to increase the internal and external conductance of the PTHs, thereby providing decreased impedance discontinuity of the signals in electronic packages.

Reducing impedance discontinuity in packages

A computer-implemented method provides an elastic modulus map of a chip carrier of a flip chip package. Design data including dielectric and conductive design elements of each of vertically aligned sub-areas of each of the layers of the chip carrier are modeled as springs to provide the elastic modulus map. Determining the elastic modulus of the sub-areas of the chip carrier identifies probable mechanical failure sites during chip-join and cools down of the flip chip package. Modifying a footprint of solder bumps to the chip carrier reduces stresses applied to the identified probable mechanical failure sites. Modifying the chip carrier design to reduce a stiffness of sub-areas associated with identified probable mechanical failure sites also reduces stresses from chip-join and cool-down.

Elastic modulus mapping of a chip carrier in a flip chip package

A method of fabricating a substrate via structure in a substrate/chip assembly includes steps of: disposing a center via stack for electrical interconnects in the substrate/chip assembly; and providing a plurality of stacked vias surrounding the center via stack. The plurality of stacked vias encircle the center via stack, resulting in no isolated via stacks on the structure. The plurality of stacked vias have both functional and non-functional vias.

Clustered stacked vias for reliable electronic substrates

A method, system and apparatus for coating plated through holes (PTHs) to reduce impedance discontinuity in electronic packages. PTH vias are imbedded in the core of a printed circuit board comprising a core layer, a plurality of buildup layers, a plurality of micro-vias, and a plurality of traces. Traces electrically interconnect each of the micro-vias to PTH vias, forming an electrically conductive path. PTHs are coated with a magnetic metal material, such as nickel, to increase the internal and external conductance of the PTHs, thereby providing decreased impedance discontinuity of the signals in electronic packages.

Method and apparatus to reduce impedance discontinuity in packages

A stacked via structure for reducing vertical stiffness includes: a plurality of stacked vias, each via disposed on a disc-like structure. The disc-like structure includes a platted through hole landing supporting the plurality of stacked vias. The platted through hole landing includes a compliant center zone; and spring-like stiffness-reducing connectors for connecting the compliant center zone of the platted through hole landing.

A substrate via structure for stacked vias in a substrate/chip assembly includes: a center via stack and a plurality of stacked vias clustered around the center via stack. In this structure, the center via and the surrounding vias are made of copper. Some of the surrounding vias may be non-functional vias and these may be of a different height than the functional vias.

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Endicott, NY, United States of America

Douglas Oliver Powell