Freescale Semiconductor,inc.

Motorola Corporation

Other

Freescale Semiconductors Inc.

Douglas G Mitchell

Scott M Hayes

Zhiwei Gong

George F Carney

Weng Foong Yap

Jason R Wright

Francis J Carney, Jr

Michael B Vincent

Alan J Magnus

Timothy Lee Johnson

Eric J Woolsey

Paul W Sanders

George R Leal

Michael F Petras

Chandrasekaram Ramiah

Lakshmi Narayan Ramanathan

Harry J Geyer

Ravinder K Sharma

Trung Duong

Cary B Powell

Joseph English

Kandis Mae Knoblauch

David Austin

Owen R Fay

Lianjun Liu

Jaynal Abedin Molla

Jinbang Tang

Varughese Mathew

Glenn Graham Daves

Jianwen Xu

Darrel R Frear

Justin Eugene Poarch

Stanley Craig Beddingfield

Eduard Jan Pabst

George W Marlin

Navjot Chhabra

Betty H Yeung

Glenn D Raskin

Kevin R Lish

Qing Tan

Carl E D Acosta

Embodiments of a microelectronic package including at least one trench via are provided, as are embodiments of a method for fabricating such a microelectronic package. In one embodiment, the method includes the step of depositing a dielectric layer over a first microelectronic device having a plurality of contact pads, which are covered by the dielectric layer. A trench via is formed in the dielectric layer to expose the plurality of contact pads therethrough. The trench via is formed to include opposing crenulated sidewalls having a plurality of recesses therein. The plurality of contact pads exposed through the trench via are then sputter etched. A plurality of interconnect lines is formed over the dielectric layer, each of which is electrically coupled to a different one of the plurality of contact pads.

Microelectronic packages having trench vias and methods for the manufacture thereof

Wafer level packages and methods for producing wafer level packages having delamination-resistant redistribution layers are provided. In one embodiment, the method includes building inner redistribution layers over a semiconductor die. Inner redistribution layers include a body of dielectric material containing metal routing features. A routing-free dielectric block is formed in the body of dielectric material and is uninterrupted by the metal routing features. An outer redistribution layer is produced over the inner redistribution layers and contains a metal plane, which is patterned to include one or more outgassing openings overlying the routing-free dielectric block. The routing-free dielectric block has a minimum width, length, and depth each at least twice the thickness of the outer redistribution layer.

Wafer level packages and methods for producing wafer level packages having delamination-resistant redistribution layers

Microelectronic packages having layered interconnect structures are provided, as are methods for the fabrication thereof. In one embodiment, the method includes forming a first plurality of interconnect lines in ohmic contact with a first bond pad row provided on a semiconductor. A dielectric layer is deposited over the first plurality of interconnect lines, the first bond pad row, and a second bond pad row adjacent the first bond pad row. A trench via is then formed in the dielectric layer to expose at least the second bond pad row therethrough. A second plurality of interconnect lines is formed in ohmic contact with the second bond pad row within the trench via. The second plurality of interconnect lines extends over the first bond pad row and is electrically isolated therefrom by the dielectric layer to produce at least a portion of the layered interconnect structure.

Microelectronic packages having layered interconnect structures and methods for the manufacture thereof

A semiconductor device package having pre-formed and placed through vias and a process for making such a package is provided. One or more signal conduits are placed in a holder that is subsequently embedded in an encapsulated semiconductor device package. The ends of the signal conduits are exposed and the signal conduits are then used as through package vias, providing signal-bearing pathways between interconnects or contacts on the bottom and top of the package. Holders can be provided in a variety of geometries and materials, depending upon the nature of the application. Further, multiple holders with signal conduits can be provided in a single package to provide for more complex interconnect configuration demands in, for example, system-in-a-package applications.

Semiconductor device packaging having pre-encapsulation through via formation using drop-in signal conduits

Microelectronic packages and methods for fabricating microelectronic packages are provided. In one embodiment, the method includes forming one or more redistribution layers over an encapsulated die having a frontside bond pad area and a frontside passivated non-bond pad area. The redistribution layers are formed to have a frontside opening over the non-bond pad area of the encapsulated die. A primary heat sink body is provided in the frontside opening and thermally coupled to the encapsulated die. A contact array is formed over the redistribution layers and is electrically coupled to a plurality bond pads located on the frontside bond pad area of the encapsulated die.

Microelectronic packages having frontside thermal contacts and methods for the fabrication thereof

Microelectronic packages and methods for fabricating microelectronic packages are provided. In one embodiment, the method comprises encapsulating a first semiconductor die having one or more core redistribution layers formed thereover in an outer molded body. The outer molded body has a portion, which circumscribes the core redistribution layer. One or more topside redistribution layers are produced over the core redistribution layer. A contact array is formed over the topside redistribution layer and electrically coupled to the first semiconductor die encapsulated in the outer molded body through the topside redistribution layers and the core redistribution layers.

Microelectronic packages and methods for the fabrication thereof

A method and apparatus for forming a backside contact, electrical and/or thermal, for die encapsulated in a semiconductor device package are provided. Die of varying thicknesses can be accommodated within the semiconductor device package. Embodiments of the present invention provide a conductive pedestal coupled to a backside contact of a die, where the coupling is performed prior to encapsulating the die within the package. In addition, conductive pedestals coupled to varying die within a semiconductor device package are of such a thickness that each conductive pedestal can be exposed on the back side of the package without exposing or damaging the backside of any encapsulated die. Embodiments of the present invention provide for the conductive pedestals being made of electrically or thermally conductive material and coupled to the device die contact using an electrically and/or thermally conductive adhesive.

Semiconductor device package having backside contact and method for manufacturing

Through substrate vias for back-side electrical and thermal interconnections on very thin semiconductor wafers without loss of wafer mechanical strength during manufacturing are provided by: forming desired device regions with contacts on the front surface of an initially relatively thick wafer; etching via cavities partly through the wafer in the desired locations; filling the via cavities with a conductive material coupled to some device region contacts; mounting the wafer with its front side facing a support structure; thinning the wafer from the back side to expose internal ends of the conductive material filled vias; applying any desired back-side interconnect region coupled to the exposed ends of the filled vias; removing the support structure and separating the individual device or IC assemblies so as to be available for mounting on a further circuit board, tape or larger circuit.

Methods for forming through-substrate conductor filled vias, and electronic assemblies formed using such methods

A method is used to form a packaged semiconductor device. A semiconductor device, which has an active surface, is placed in an opening of a circuit board. The circuit board has a first major surface and a second major surface having the opening, first vias that extend between the first major surface and the second major surface, first contact pads terminating the vias at the first major surface, and second contact pads terminating the vias at the second major surface. A dielectric layer is applied over the semiconductor device and the second major surface of the circuit board. An interconnect layer is formed over the dielectric layer. The interconnect layer has second vias electrically connected to the second contact pads, third vias that are electrically connected to the active surface of the semiconductor device, an exposed surface, and third contact pads at the exposed surface.

Method of forming a packaged semiconductor device

A device comprises a substrate, a micro electro-mechanical systems (MEMS) structure, and a dielectric film. The substrate has a first side and a second side, the second side opposite the first side. The MEMS structure is formed on the first side of the substrate. The cavity is formed in the substrate directly opposite the MEMS structure. The cavity has an opening formed on the second side. The dielectric film is attached to the second side of the substrate and completely covering the opening. In one embodiment, the MEMS structure is a diaphragm for a microphone. Another embodiment includes a method for forming the device.

MEMS microphone with cavity and method therefor

An integrated conformal electromagnetic interference (EMI) and/or electromagnetic radiation shield is formed on a plurality of encapsulated modules by attaching a plurality of modules (-) to a process carrier () using a double side adhesive tape (), and then sequentially depositing an insulating layer () and a conductive shielding layer () before encapsulating the modules with a molding compound (). After removing the adhesive tape () to expose a surface of the encapsulated modules, a multi-layer circuit substrate () is formed over the exposed surface, where the circuit substrate includes shielding via structures (-) that are aligned with and electrically connected to the conductive shielding layer (), thereby encircling and shielding the circuit module(s).

Integrated conformal shielding method and process using redistributed chip packaging

A method is disclosed for controlling warpage in an integrated electronic panel assembly including a plurality of die embedded within an encapsulant. The method comprises determining a number of build-up layers required for the integrated panel assembly. Each build-up layer contributes an amount of concavity to the integrated electronic panel assembly. A level of global convex warpage on the integrated panel assembly is then predicted, wherein the global convex warpage is provided by the presence of an embedded ground plane (EGP) alone within the integrated panel assembly and in the absence of any build-up layers. The embedded ground plane includes openings therein for accepting at least one die within a corresponding opening and it contributes a fixed amount of global convex warpage. An amount of local convex warpage to be introduced into the integrated electronic panel assembly is then determined, which together with the fixed amount of global convex warpage provides a combined convex warpage to the integrated electronic panel assembly. Accordingly, the global and local convex warpage counteract the concavity to be introduced subsequently by a build-up layer processing and is sufficient to enable subsequent planar processing of a completed integrated electronic panel assembly.

Method for controlling warpage in redistributed chip packaging panels

Through substrate vias for back-side electrical and thermal interconnections on very thin semiconductor wafers without loss of wafer mechanical strength during manufacturing are provided by: forming () desired device regions () with contacts () on the front surface () of an initially relatively thick wafer ('); etching () via cavities () partly through the wafer (&#x2032;) in the desired locations; filling () the via cavities () with a conductive material () coupled to some device region contacts (); mounting () the wafer (&#x2032;) with its front side () facing a support structure (); thinning () the wafer (&#x2032;) from the back side () to expose internal ends (, etc.) of the conductive material filled vias (, etc.); applying () any desired back-side interconnect region () coupled to the exposed ends (, etc.) of the filled vias; removing () the support structure () and separating the individual device or IC assemblies () so as to be available for mounting () on a further circuit board, tape or larger circuit ().

Through substrate vias for back-side interconnections on very thin semiconductor wafers

Methods and apparatus are provided for encapsulating electronic devices, comprising: providing one or more electronic devices () with primary faces () having electrical contacts (), opposed rear faces () and edges () therebetween. A sacrificial layer () is provided on the primary faces (). The devices () are mounted on a temporary support () so that the sacrificial layer () faces toward the temporary support (). A plastic encapsulation ()is formed in contact with at least the lateral edges () of the electronic devices (). The plastic encapsulation () is at least partially cured and the devices () and plastic encapsulation () separated from the temporary support (), thereby exposing the sacrificial layer (). The sacrificial layer () is removed. The devices () and edge-contacting encapsulation are mounted on a carrier () with the primary faces () and electrical contacts () exposed and, optionally, further cured. Insulators () and conductors () applied to the primary faces couple electrical contacts () on various devices () to each other and to external contacts, thereby forming an integrated multi-device panel ().

Semiconductor device packaging

A structure and method for achieving a flip-chip semiconductor device having plated copper inductors (), transformers (), interconnect, and power busing that is electrically superior, lower cost, and provides for higher quality inductors as well as lower losses for on-chip transformers. Providing a solder dam () enables the fabrication of flip-chip solder bumps directly on to inductors and transformers.

Flip-chip structure and method for high quality inductors and transformers

Growing community of inventors

Tempe, AZ, United States of America

Douglas G Mitchell