Silicon Laboratories Inc.

Cirrus Logic Inc.

Skyworks Solutions, Inc.

Crystal Semiconductor Corporation

Douglas F Pastorello

Timothy A Monk

Eric T King

Golam Rasul Chowdhury

Biranchinath Sahu

Lizhong Sun

Axel Thomsen

Raghunandan Kolar Ranganathan

Krishnan Balakrishnan

William Gardei

Richard J Juhn

Michael Henderson Perrott

Douglas R Holberg

Bruce Philip Del Signore

Jerome E Johnston

Akhil K Garlapati

William Durbin

Patrick De Bakker

Rajesh Thirugnanam

Louis J Nervegna

Qicheng Yu

Frank Den Breejen

Joe White

Saibun Wong

Ping Lu

Michael Lu

Victor Aguilar

A clock product includes a time-to-digital converter responsive to an input clock signal, a reference clock signal, and a time-to-digital converter calibration signal. The time-to-digital converter includes a coarse time-to-digital converter and a fine time-to digital converter. The clock product includes a calibration circuit including a phase-locked loop. The calibration circuit is configured to generate the time-to-digital converter calibration signal. The clock product includes a controller configured to execute instructions that cause the phase-locked loop to generate an error signal for each possible value of a fine time code of a digital time code generated by the time-to-digital converter and to average the error signal over multiple clock cycles to generate an average error signal.

Calibration of a time-to-digital converter using a virtual phase-locked loop

In at least one embodiment, a method includes generating a digital time code corresponding to an input clock signal using a time-to-digital converter responsive to a reference clock signal and a time-to-digital converter calibration signal. The method includes generating the time-to-digital converter calibration signal based on the digital time code. Generating the time-to-digital converter calibration signal includes generating a digital error signal based on the digital time code and an estimated digital time code, and adapting the time-to-digital converter calibration signal based on the digital error signal.

A clock generator includes an interpolative divider including a phase interpolator and a multi-modulus divider. The interpolative divider is configured to generate an output clock signal based on a clock signal, a control code, and a phase interpolator calibration signal. The clock generator includes a calibration circuit configured to generate the phase interpolator calibration signal based on the clock signal, the output clock signal and a phase interpolator code. The calibration circuit includes a phase-locked loop configured to generate a digital phase error signal based on a reference timestamp signal and a timestamp signal based on the clock signal and the output clock signal. The calibration circuit includes an adaptive loop configured to generate the phase interpolator calibration signal based on the digital phase error signal.

Calibration of an interpolative divider using a virtual phase-locked loop

A spur target frequency is periodically determined to cancel a spur using a spur cancellation circuit in a first phase-locked loop (PLL) in a system with at least a second PLL that is in lock with the first PLL. The spur target frequency is periodically determined utilizing divide ratios of the first PLL and the second PLL to determine the updated spur target frequency. As one or more of the divide ratios change, the spur frequency changes and the spur target frequency is updated to reflect the change.

Spur cancellation in a PLL system with an automatically updated target spur frequency

A chip having output synchronization includes a phase detector for receiving an external reference clock signal, an input delay path coupled to an output of the phase detector and having an output for providing an internal reference clock signal, an output delay path coupled to the output of the input delay path and having an output coupled to a feedback input of the phase detector, a phase adjustment circuit having a first input coupled to the output of the input delay path, a second input for receiving a local clock signal, and an output coupled to the control input of the input delay path, and a synchronization capture circuit having a first input coupled to the output of said input delay path, a second input for receiving the local clock signal, a third input for receiving a synchronization signal, and an output for providing a synchronization trigger signal.

Metastable-free output synchronization for multiple-chip systems and the like

A feedback loop includes an oscillator-based analog-to-digital converter configured to convert an analog signal to a first digital value and a second digital value. The oscillator-based analog-to-digital converter includes a first oscillator having a first oscillation frequency configured to generate a first digital value based on a first signal component of the analog signal. The oscillator-based analog-to-digital converter includes a second oscillator having a second oscillation frequency configured to generate a second digital value based on a second signal component of the analog signal. The first and second signal components are complementary signal components. The feedback loop includes a combiner configured to generate a digital value based on the first digital value, the second digital value, and an offset code. The offset code has a value that increases a difference between the first oscillation frequency and the second oscillation frequency.

Differential voltage-controlled oscillator analog-to-digital converter using input-referred offset

The present invention comprises a microcontroller unit including a processor for generating a power down signal. Control logic generates a hold signal responsive to the power down signal. A voltage regulator provides a regulated voltage responsive to an input voltage and powers down responsive to the power down signal. At least one digital device powered by the regulated voltage enters a powered down mode responsive to the voltage regulator entering the powered down state. The at least one digital device provides at least one digital output signal that is provided to an input/output cell. The input/output cell also is connected to receive a hold signal. The input/output cell maintains a last state of the digital output signal responsive to the hold signal when the at least one digital device enters the powered down state.

Programmable I/O cell capable of holding its state in power-down mode

A memory power controller comprises a clock generation circuitry for generating a first clock signal and a second clock signal responsive to a source clock and a determination that the source clock has a period greater than a predetermined value. The first clock is generated responsive to a determination that the source clock has a period greater than the predetermined value and the second clock is generated responsive to the determination that the source clock has a period less than the predetermined value. Memory time-out circuitry generates a memory enable/disable signal to control operation of an associated memory responsive to the clock signal and the determination that the source clock has a period greater than the predetermined value. The memory time-out circuitry further synchronizes the memory enable/disable signal with the source clock.

Memory power controller

A microcontroller unit includes a processor for generating a first control signal to start a comatose mode of operation for the microcontroller unit. Control logic responsive to the first control signal generates an enable signal at a first level and the control logic is further responsive to a second control signal for generating the enable signal at a second level. A voltage regulator generates regulated voltage from an input voltage. The voltage regulator shuts down to provide a zero volt regulated voltage responsive to the enable signal at the first level and powers up to provide a regulated voltage at an operating level responsive to the enable signal at the second level.

Microcontroller unit (MCU) with power saving mode

A technique for increasing functionality of terminals of an integrated circuit without increasing the number of terminals of the integrated circuit utilizes at least one tri-level terminal and converter circuit that provides a logic level indicative of a test mode of the integrated circuit in response to a corresponding input level. The technique substantially reduces or eliminates false detections of the test mode and substantially reduces or eliminates falsely enabling other (e.g., functional) mode(s) of the integrated circuit.

Tri-level test mode terminal in limited terminal environment

A method for dividing a signal having a first frequency by a divide ratio includes selecting, based on the divide ratio, a first pulse width of at least one signal having a second frequency and being generated by at least a corresponding one of a plurality of pulse-width control circuits responsive to at least one signal having a second pulse width. The method includes selecting at least one of the plurality of pulse-width control circuits to be powered-on to generate the at least one signal. The at least one of the plurality of pulse-width control circuits includes a first pulse-width control circuit to generate a first signal having the first pulse-width, second frequency, and first phase. The first signal corresponds to a select circuit output signal having a first phase. The method includes selecting at least one other of the plurality of pulse-width control circuits to be powered-off.

High-speed divider with reduced power consumption

A frequency detector and frequency-locked loop suitable for use in a clock recovery circuit are disclosed. The detector is linear, and can be used in implementing a loss of lock indicator. Variable delay filtering permits the frequency detector to be less sensitive to data fluctuations, and random or pseudo random addition of jitter helps address low gain in the data stream. A VCO controller cycles through a number of control states and provides varying levels of gain, dither and delay during each of the control states.

Frequency detector including a variable delay filter

MCU with power saving mode

In at least one embodiment of the invention, a method for dividing a first signal having a first frequency by a divide ratio to generate a lower frequency signal includes generating a first plurality of signals having a common frequency, a first pulse width, and different phases. The first plurality of signals is based, at least in part, on at least one signal having a second pulse width. The first pulse width is selected from a plurality of pulse widths based, at least in part, on the divide ratio. The method includes sequentially selecting individual pulses of the first plurality of signals as an output signal of a select circuit to generate an output signal having a frequency lower than the first frequency.

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Hudson, NH, United States of America

Douglas F Pastorello