Siemens Aktiengesellschaft

Infineon Technologies Ag

Technische Universitaet Muenchen

Doris Schmitt-Landsiedel

Roland Thewes

Paul-Werner Von Basse

Michael Bollu

Thomas Nirschl

Stephan Henzler

Christian Pacha

Georg Georgakos

Werner Weber

Ronald Kakoschke

Jörg Berthold

Gerhard Dorda

Gerd Neuendorf

Maria Wurm

Bernhard Hoppe

Thomas Schulz

Hans-Joerg Pfleiderer

Klaus Schruefer

Gerhard Nebel

Joerg Berthold

Juergen Holz

Andreas Luck

Hans-Juergen Mattausch

Robert Reiner

Bernhard Wicht

Wolfgang H Krautschneider

Gerhard Schraud

Jean-Yves Larguier

Jens Sauerbrey

Erdmute Wohlrab

Werner M Klingenstein

Ute Kollmer

Matthias Schobinger

Josef Kiermaier

Volker G&uuml;ngerich

Andreas Luck, Deceased

Doktorand Andreas Luck

Doris Keitel-Schulz

Steffen Becker

Markus Becherer

Vincent Frechet

Stephen Breitkreutz

Thomas Tille

Irina Eichwald

By Inge Booken, Legal Representative

By Manfred Luck, Legal Representative

Integrated circuit arrangement comprising a field effect transistor, especially a tunnel field effect transistor. An explanation is given of, inter alia, tunnel field effect transistors having a thicker gate dielectric in comparison with other transistors on the same integrated circuit arrangement. As an alternative or in addition, said tunnel field effect transistors have gate regions at mutually remote sides of a channel forming region or an interface between the connection regions of the tunnel field effect transistor.

Integrated circuit arrangement comprising a field effect transistor, especially a tunnel field effect transistor

A nanomagnetic logic gate arranged on a substrate according to an embodiment includes at least one nanomagnetic first structure, at least one nanomagnetic second structure and at least two layers including a first layer and a second layer, wherein at least one first structure is arranged in the first layer on or parallel to a main surface of the substrate, wherein at least one second structure is arranged in the second layer parallel to the first layer, and wherein at least one second structure includes an artificial nucleation center arranged such that a magnetic field component essentially perpendicular to the main surface provided by at least one first structure couples to the artificial nucleation center such that a magnetization of the second structure is changeable in response to the magnetic field component coupled into the artificial nucleation center, when a predetermined condition is fulfilled.

Nanomagnetic logic gate and an electronic device

An explanation is given of, inter alia, tunnel field effect transistors having a thicker gate dielectric (GD) in comparison with other transistors (T) on the same integrated circuit arrangement (). As an alternative or in addition, said tunnel field effect transistors have gate regions at mutually remote sides of a channel forming region or an interface between the connection regions (D, S) of the tunnel field effect transistor.

An integrated circuit includes functional blocks, a power control unit controlling the provision of power to the different functional blocks of the integrated circuit, a detecting unit detecting if a turned off functional block is to be turned on, and a clock signal control unit controlling the provision of the clock signal for the functional blocks. The clock signal control unit interrupts the clock signal for the activated functional blocks of the integrated circuit for a predetermined number of clock cycles. The power control unit provides power to the turned off functional block during the interrupted clock cycles.

Circuit arrangement for activating a circuit block and method for the same

An intergrated circuit having a drive circuit is disclosed. One embodiment provides an intergrated memory circuit arrangement with a drive circuit for an EEPROM. In one embodiment, the drive circuit contains tunnel field effect transistors and can be produced in particular on a small chip area.

Integrated circuit having a drive circuit

The flip-flop according to the invention serves for storing an item of logic state information and has at least one data input and at least one data output. The flip-flop comprises at least one latch stage for storing the state information if the flip-flop is switched on. Furthermore, the flip-flop according to the invention comprises at least one memory cell having a capacitance as storage element. In this case, the at least one memory cell serves for storing the state information if the flip-flop is switched off.

Flip-flop with additional state storage in the event of turn-off

A method and an apparatus for switching on a voltage supply of a voltage domain of a semiconductor circuit is disclosed. A voltage supply is connected to a supply voltage of the semiconductor circuit by means of a switchable element. The switchable element is activated in such a way that, for switching on the voltage supply of the voltage domain, a current through the switchable element rises progressively with at least one intermediate value, in particular stepwise manner.

Method and apparatus for switching on a voltage supply of a semiconductor circuit and corresponding semiconductor circuit

Logic activation circuit for switching a logic circuit having at least one supply voltage line on or off, said logic activation circuit having:

Logic activation circuit

A differential current evaluation circuit has a differential amplifier and a circuit for setting an input resistance of the current evaluation circuit. The circuit is connected to the outputs and the inputs of the differential amplifier and to signal lines. A sense amplifier circuit has a circuit section, in which a signal is available at an output in a temporally continuous manner even if, after the deactivation of the circuit connected upstream, a signal, in particular a signal supplied by the current evaluation circuit, is no longer present at its input. The differential current evaluation circuit and the sense amplifier circuit are disposed in a circuit configuration for reading out and evaluating a memory state of a semiconductor memory cell. The current evaluation circuit can be activated by a circuit section for automatic deactivation before a read operation and be automatically deactivated directly after the read operation has ended.

Differential current evaluation circuit and sense amplifier circuit for evaluating a memory state of an SRAM semiconductor memory cell

A circuit configuration for providing a capacitance includes short-channel MOS transistors that are reverse-connected in series or in parallel, and that have the same channel type. When the short-channel MOS transistors are operated exclusively in the depletion mode in the required voltage range, the useful capacitance is increased, because of intrinsic capacitances, as compared with circuit configurations having conventional long-channel MOS transistors. These circuits greatly reduce the area taken up and reduce the costs.

Circuit configuration for forming a MOS capacitor with a lower voltage dependence and a lower area requirement

A data carrier includes at least one coil for the contactless reception of amplitude-modulated signals. A rectifier circuit is connected downstream of the coil. A circuit configuration processes and/or stores data. A supply-voltage control circuit is connected in parallel with the circuit configuration. A current measuring device acts as an amplitude demodulator and is disposed between the coil and the voltage-supply control circuit.

Data carrier for the contactless reception of amplitude-modulated signals

A circuit with a delay stage formed by an invertor having high-impedance transistors and, connected in series therewith, an invertor having low-impedance transistors MOS capacitors are provided between the gates of the transistors of the low-impedance invertor and the output of the delay stage. By means of this circuit, delay stages with steep edges can be realized with comparatively less outlay on components.

Steep edge time-delay relay

Device for the jump-like addressing of specific lines of a serially

In the pointer circuit, only one static memory (1) is respectively individually allocated to each output ( . . . , A.sub.n-1, A.sub.n, A.sub.n+1, . . . ), of which each respectively has a pair of mutually complementary memory terminals (Q, Q). The two terminals are in two stored logical states ('1,' '0') differing from one another. A memory terminal (Q) of each memory is connected with the output allocated to this memory. The memories are controlled by clock signals. This results in advantageous surface requirement and power loss low, as well as high speed.

Pointer circuit with low surface requirement high speed and low power

A digital/analog converter has a neuron MOS transistor, a maintenance circuit which keeps the drain potential of the neuron MOS transistor constant, and a current source. A linear dynamic range in terms of large signal is possible, so that converters having a larger input word size than, for example, only two bits can be realized in a simple way with low dissipated power. Such converters are of significance particularly for ULSI circuits.

Digital/analog converter using a floating gate MOS neuron transistor

Growing community of inventors

Ottobrunn, Germany

Doris Schmitt-Landsiedel