Samsung Electronics Co., Ltd.

Doohyun Lee

Heonjong Shin

Minchan Gwak

Sunghun Jung

Yongsik Jeong

Sangwon Jee

Hyunho Park

Sora You

Jinyoung Park

Inchan Hwang

Yeongchang Roh

Hyun-Seung Song

Hwichan Jun

Seon-Bae Kim

Seonbae Kim

Sungmoon Lee

Hakyoon Ahn

Sungmin Kim

A semiconductor device includes active regions extending in a first direction on a substrate; a gate electrode intersecting the active regions on the substrate, extending in a second direction, and including a contact region protruding upwardly; and an interconnection line on the gate electrode and connected to the contact region, wherein the contact region includes a lower region having a first width in the second direction and an upper region located on the lower region and having a second width smaller than the first width in the second direction, and wherein at least one side surface of the contact region in the second direction has a point at which an inclination or a curvature is changed between the lower region and the upper region.

Semiconductor device

A semiconductor device is provided. The semiconductor device includes: an active pattern provided on a substrate having an upper surface; an insulation pattern provided above the substrate and contacting an upper surface of the active pattern; channels spaced apart from each other along a direction perpendicular to the upper surface of the substrate, each of the channels including a material provided in the active pattern; and a gate structure contacting an upper surface of the insulation pattern, an upper surface of the channels, a lower surface of the channels, and sidewalls of the channels opposite to each other. A first distance between an upper surface of the active pattern and a lowermost one of the channels is greater than a second distance between an upper surface of one of the channels and a lower surface of an adjacent channel.

Multi-bridge channel field effect transistor with reduced gate-channel leakage current

A semiconductor device may include first and second active regions on a substrate, first and second active patterns on the first and second active regions, first and second source/drain patterns on the first and second active patterns, first and second silicide patterns on the first and second source/drain patterns, and first and second active contacts coupled to the first and second source/drain patterns. A lowermost portion of the first active contact is at a level higher than that of a lowermost portion of the second active contact. A thickness of the first silicide pattern is greater than that of the second silicide pattern.

A semiconductor device may include an active pattern on a substrate, a source/drain pattern on the active pattern, a channel pattern connected to the source/drain pattern, a gate electrode on the channel pattern, an active contact on the source/drain pattern, a first lower interconnection line on the gate electrode, and a second lower interconnection line on the active contact and at the same level as the first lower interconnection line. The gate electrode may include an electrode body portion and an electrode protruding portion, wherein the electrode protruding portion protrudes from a top surface of the electrode body portion and is in contact with the first lower interconnection line thereon. The active contact may include a contact body portion and a contact protruding portion, wherein the contact protruding portion protrudes from a top surface of the contact body portion and is in contact with the second lower interconnection line thereon.

A method of manufacturing a semiconductor device includes forming an active region on a substrate, forming a gate structure on the substrate intersecting the active region, removing an upper portion of the gate structure and forming a gate capping layer, forming a preliminary contact plug electrically connected to a portion of the active region, the preliminary contact plug including first and second portions, forming a mask pattern layer including a first pattern layer covering an upper surface of the gate capping layer, and a second pattern layer extending from the first pattern layer to cover the second portion of the preliminary contact plug, and forming a contact plug using the mask pattern layer as an etch mask by recessing the first portion of the preliminary contact plug exposed by the mask pattern layer to a predetermined depth from an upper surface of the preliminary contact plug.

Semiconductor device having a source/drain contact plug with an upwardly protruding portion

A semiconductor device comprising a gate electrode on a substrate, a source/drain pattern on the substrate on a side of the gate electrode, and a gate contact plug on the gate electrode are disclosed. The gate contact plug may include a first gate contact segment, and a second gate contact segment that extends in a vertical direction from a top surface of the first gate contact segment. An upper width of the first gate contact segment may be greater than a lower width of the second gate contact segment.

Method of fabricating semiconductor devices including a fin field effect transistor

A semiconductor device including: a substrate that includes a first active region and a second active region; a first source/drain pattern on the first active region; a second source/drain pattern on the second active region; a separation dielectric pattern on the substrate between the first source/drain pattern and the second source/drain pattern; and a first contact pattern on the first source/drain pattern, wherein the first contact pattern includes: a first metal pattern; a first barrier pattern between the first metal pattern and the first source/drain pattern; and a second barrier pattern between the first barrier pattern and the first source/drain pattern, wherein the first barrier pattern contacts the separation dielectric pattern and extends along a sidewall of the first metal pattern adjacent to the separation dielectric pattern.

A semiconductor device may include a substrate including an active pattern extending in a first direction, a gate electrode running across the active pattern and extending in a second direction intersecting the first direction, a source/drain pattern on the active pattern and adjacent to a side of the gate electrode, an active contact in a contact hole exposing the source/drain pattern, an insulating pattern filling a remaining space of the contact hole in which the active contact is provided, a first via on the active contact, and a second via on the gate electrode. The active contact may include a first segment that fills a lower portion of the contact hole and a second segment that vertically protrudes from the first segment. The first via is connected to the second segment. The insulating pattern is adjacent in the first direction to the second via.

Active regions via contacts having various shaped segments off-set from gate via contact

A semiconductor device is disclosed. The semiconductor device may include a substrate including a first active pattern, the first active pattern vertically protruding from a top surface of the substrate, a first source/drain pattern filling a first recess, which is formed in an upper portion of the first active pattern, a first metal silicide layer on the first source/drain pattern, the first metal silicide layer including a first portion and a second portion, which are located on a first surface of the first source/drain pattern, and a first contact in contact with the second portion of the first metal silicide layer. A thickness of the first portion may be different from a thickness of the second portion.

Growing community of inventors

Hwaseong-si, South Korea

Doohyun Lee