Samsung Electronics Co., Ltd.

Doo-Gon Kim

Ki-Tae Park

Yeong-taek Lee

Myoung-gon Kang

Ki-Nam Kim

Jung-bae Lee

Byung-Gil Jeon

Yoon-Ho Khang

Dong-Hyuk Lee

Han-gu Sohn

Cheol Su Kim

Duk-Ha Park

Youn-Cheul Kim

Sei-jin Kim

Hui-kwon Seo

Cheol-kyu Kim

Tae-yon Lee

Dae-won Ha

A leakage current detection device includes a test detection circuit, a reference detection circuit, a comparator, and a latch circuit. The test detection circuit is coupled between a test node and a test line, provides a voltage to the test node to charge the test line, floats the test node and the test line, and decreases a voltage of the test node based on leakage current of the test line. The reference detection circuit is coupled between a reference node and a reference line, provides the voltage to the reference node to charge the reference line, floats the reference node and the reference line, and decreases a voltage of the reference node based on self-discharge of the reference line. The comparator outputs a comparison signal by comparing voltages of the test node and the reference node. The latch circuit latches the comparison signal to output a test result signal.

Leakage current detection device and nonvolatile memory device having the same

A memory system includes a memory cell array having a plurality of memory sectors. Each memory sector includes a plurality of memory cells. The memory system further includes a controller configured to write data to the memory cell array in response to a writing signal. The controller is further configured to refresh a memory sector among the plurality of memory sectors each time a writing signal is provided. When N (N is a positive integer) memory cells are programmed, a programming current is less than or equal to about 0.75 mA*N.

Memory controllers to refresh memory sectors in response to writing signals and memory systems including the same

An erasing method of post-programming in a nonvolatile memory device. The method includes post-programming dummy memory cells; verifying whether threshold voltages of the dummy memory cells are greater than or equal to a first voltage; post-programming normal memory cells; and verifying whether threshold voltages of the normal memory cells are greater than or equal to a second voltage. The first voltage is different from the second voltage.

Method of erasing in non-volatile memory device

A semiconductor memory device includes a cell array unit having a plurality of banks each having a plurality of blocks, and a refresh controller configured to set at least one of the blocks as a test block, perform a refresh operation on the blocks except for the test block in a self-refresh operation period, determine a refresh period of the test block, and then set another one of the blocks as the test block.

Semiconductor memory device and system including the same

A nonvolatile memory device includes a three-dimensional (3D) cell array, a column selection circuit and a fuse block. The 3D cell array includes multiple cell arrays located in corresponding stacked substrate layers, the cell arrays sharing a bit line. The column selection circuit selects a memory unit included in the 3D cell array. The fuse block controls the column selection circuit to repair defective columns with one of multiple redundant bit lines located in the 3D cell array.

Semiconductor memory device with three-dimensional array and repair method thereof

An erasing method in a nonvolatile memory device is disclosed. The method includes post-programming dummy memory cells; verifying whether threshold voltages of the dummy memory cells are greater than or equal to a first voltage; post-programming normal memory cells; and verifying whether threshold voltages of the normal memory cells are greater than or equal to a second voltage. The first voltage is different from the second voltage, and the post-programming of the dummy memory cells comprises: applying a program voltage to a plurality of dummy word lines coupled to the dummy memory cells to post-program the dummy memory cells; and applying a pass voltage to a plurality of normal word lines coupled to the normal memory cells so that the normal memory cells are not post-programmed.

A flash memory device includes first and second memory cell array blocks and a row decoder coupled to the first memory cell array block and the second memory cell array block. The row decoder includes a block decoder, a single high voltage level shifter that is coupled to both the first and second memory cell array blocks, the single high voltage level shifter configured to provide a block wordline signal of a high voltage to the first and second memory array blocks in response to a block selection signal received from the block decoder, a first pass transistor unit, and a second pass transistor unit.

Flash memory device having row decoders sharing single high voltage level shifter, system including the same, and associated methods

Non-volatile memory devices and methods of programming the non-volatile memory devices use six threshold voltage levels. Data also may be read from the non-volatile memory devices. The non-volatile memory devices include a first non-volatile memory cell and a second non-volatile memory cell, each of which can be programmed with first through sixth threshold voltage levels that sequentially increase. Programming includes first, second and third data bit program operations. In the first and second data bit program operation, the first and second non-volatile memory cells are programmed with the first or second threshold voltage level in order to store first and second bits of data. In the third data bit program operation, the first non-volatile memory cell is programmed with the third or fourth threshold voltage level according to the first and second bits of the data in order to store a third bit of the data. Fourth and fifth data bit program operations also may be provided.

Programming and reading five bits of data in two non-volatile memory cells

Flash memory devices are provided including a plurality of layers stacked vertically. Each of the plurality of layers include a plurality of memory cells. A row decoder is electrically coupled to the plurality of layers and configured to supply a wordline voltage to the plurality of layers. Memory cells provided in at least two layers of the plurality of layers belong to a same memory block and wordlines associated with the memory cells in the at least two layers of the plurality of layers are electrically coupled.

Flash memory devices having three dimensional stack structures and methods of driving same

A non volatile memory device and method of operating including providing a verification voltage to a gate of a selected memory cell within multiple memory cells and providing a first pass voltage to a gate of a non-selected memory cell within the memory cells during a program verification operation; and providing a read voltage to the gate of the selected memory cell and providing a second pass voltage to the gate of the non-selected memory cell during a read operation. The second pass voltage is greater than the first pass voltage.

Non-volatile memory device and method of operating

Provided are methods for programming in a non-volatile memory device, using incremental step pulses as a program voltage that is applied to a selected wordline. Methods may include applying a precharge voltage to an even bitline and an odd bitline such that the even bitline and the odd bitline are alternately charged with the precharge voltage and a boosted voltage that is higher than the precharge voltage. Methods may further include applying a bitline voltage corresponding to program data to a selected bitline of the even bitline and the odd bitline.

Method of programming in a non-volatile memory device and non-volatile memory device for performing the same

A flash memory device includes; a plurality of layers, each one including memory cells arranged in a matrix of rows and columns, a layer decoder configured to select one of the plurality of layers to thereby define a selected layer and an unselected layer, a voltage generator configured to generate an erase voltage at a level higher than ground voltage, and an internal voltage, and a row select circuit configured to apply the erase voltage to the selected layer, and apply at least one of the erase voltage and the internal voltage to the unselected layer during an erase operation.

Flash memory device applying erase voltage

Provided are a semiconductor memory device and a method of generating a chip enable signal thereof. The device includes a plurality of memory chips and an interface chip that are stacked. Each of the memory chips includes a control signal setting unit, which sets input signals applied to first and second input nodes as less significant 2-bit control signals of n-bit control signals, performs a logic AND operation on the less significant 2-bit control signals to generate AND operated signals, performs a logic XOR operation on each of the AND operated signals and each bit signal of more significant n&#x2212;2-bit input signals applied to third to n-th input nodes to set the n&#x2212;2-bit control signals, outputs the signal applied to the second input node through a first output node, inverts the signal applied to the first input node to output the inverted signal through a second output node, and outputs the more significant n&#x2212;2-bit input signals through third through n-th output nodes, respectively. The first through n-th output nodes of one of two adjacent memory chips are respectively connected to the first through n-th input nodes of the other of the two adjacent memory chips.

Semiconductor memory device and method of generating chip enable signal thereof

Embodiments of the invention include a semiconductor memory device and a method for operating the semiconductor memory device. The invention includes a semiconductor memory device comprising a memory cell array block including a plurality of first memory cells connected to a plurality of first bit lines and a plurality of second memory cells connected to a plurality of second bit lines. The semiconductor memory device further includes a first sensing block disposed on a first side of the memory cell array block, a second sensing block disposed on a second side of the memory cell array block, and a control unit receiving a sensing block selection address signal, wherein, when the sensing block selection address signal specifies the first sensing block, the control unit enables the first sensing block and disables the second sensing block.

Growing community of inventors

Gyeonggi-do, South Korea

Doo-Gon Kim