Stats Chippac Pte. Ltd.

DongSam Park

KyungOe Kim

Choong Bin Yim

Dongjin Jung

YongDuk Lee

Jaehyun Lim

SeongMin Lee

Sungmin Song

A Leam Choi

JoungIn Yang

Joungin Yang

Wagno Alves Braganca, Jr

Joungln Yang

HeeJo Chi

HanGil Shin

In Sang Yoon

Sang-Ho Lee

YoungSik Cho

Keon Teak Kang

WooJin Lee

A semiconductor device has a heat spreader with an opening formed through the heat spreader. The heat spreader is disposed over a substrate with a semiconductor die disposed on the substrate in the opening. A thermally conductive material, e.g., adhesive or an elastomer plug, is disposed in the opening between the heat spreader and semiconductor die. A conductive layer is formed over the substrate, heat spreader, and thermally conductive material.

Thermally enhanced FCBGA package

A semiconductor device has a substrate and two semiconductor die disposed over the substrate. A thermal interface material is disposed over the semiconductor die. A conductive epoxy is disposed on a ground pad of the substrate. A lid is disposed over the semiconductor die. The lid includes a sidewall over the ground pad between the semiconductor die. The lid physically contacts the conductive epoxy and thermal interface material.

Package with compartmentalized lid for heat spreader and EMI shield

A semiconductor device has a substrate with a first conductive layer over a surface of the substrate and a plurality of cavities exposing the first conductive layer. A first semiconductor die having conductive TSV is mounted into the cavities of the substrate. A first insulating layer is formed over the substrate and first semiconductor die and extends into the cavities to embed the first semiconductor die within the substrate. A portion of the first insulating layer is removed to expose the conductive TSV. A second conductive layer is formed over the conductive TSV. A portion of the first conductive layer is removed to form electrically common or electrically isolated conductive segments of the first conductive layer. A second insulating layer is formed over the substrate and conductive segments of the first conductive layer. A second semiconductor die is mounted over the substrate electrically connected to the second conductive layer.

Semiconductor device and method of embedding TSV semiconductor die within substrate for vertical interconnect in POP

A method of manufacture of an integrated circuit packaging system includes: providing a substrate; mounting an integrated circuit over the substrate; forming an encapsulation over the integrated circuit, the encapsulation having an encapsulation interior sidewall; forming a peripheral non-horizontal conductive plate directly on the encapsulation interior sidewall; and forming a peripheral vertical conductor directly on the peripheral non-horizontal conductive plate and the substrate.

Integrated circuit packaging system with vertical interconnects and method of manufacture thereof

A semiconductor device has a carrier or first conductive layer with a plurality of TSV semiconductor die mounted over the carrier or first conductive layer. An encapsulant is deposited around the first semiconductor die and over the carrier or first conductive layer to embed the first semiconductor die. A conductive TMV is formed through the encapsulant. A second conductive layer is formed over a first surface of the encapsulant. A first insulating layer is formed over the first surface of the encapsulant while exposing portions of the second conductive layer. A second insulating layer is formed over the second surface of the encapsulant while exposing portions of the first conductive layer. Alternatively, a first interconnect structure is formed over the first surface of the encapsulant. The carrier is removed and a second interconnect structure is formed over a second surface of the encapsulant.

Semiconductor device and method of embedding TSV semiconductor die within encapsulant with TMV for vertical interconnect in POP

An integrated circuit packaging system includes: a carrier, having a carrier top side and a carrier bottom side, without an active device attached to the carrier bottom side; an interconnect over the carrier; and a first encapsulation, having a cavity, around the interconnect over the carrier top side with the interconnect partially exposed from the first encapsulation, and with the carrier top side partially exposed with the cavity.

Integrated circuit packaging system having a cavity

A method of manufacture of a package-on-package system includes: providing a substrate connection; attaching a semiconductor die to the substrate connection using an adhesive, with the substrate connection affixed directly by the adhesive; forming an encapsulant around the semiconductor die to have a bottom exposed surface coplanar with a bottom surface of the substrate connection and to have a top exposed surface with through openings extending therefrom through the bottom exposed surface; and creating through vias by applying solder into the through openings, the through vias coplanar with the bottom exposed surface of the encapsulant and coplanar with the top exposed surface of the encapsulant.

Package-on-package system with through vias and method of manufacture thereof

A method of manufacture of an integrated circuit packaging system includes: providing a stack substrate with a component side; connecting an integrated circuit component to the component side; attaching a conductive post to the component side and adjacent the integrated circuit component, the conductive post having a protruded end above the integrated circuit component; forming a protection layer on a top and sides of the protruded end, the protection layer having a width equal to a width of the conductive post; applying a stack encapsulation over the integrated circuit component, over the stack substrate, and around a portion of the conductive post, the protection layer exposed from the stack encapsulation; and mounting a base package under the stack substrate, base package connected to the stack substrate.

Integrated circuit packaging system with post and method of manufacture thereof

A integrated circuit package on package system is provided including providing a base substrate having a base stackable connection, attaching a base integrated circuit on the base substrate, forming a stackable package including the base integrated circuit encapsulated with the base stackable connection partially exposed, and attaching a bottom package on the stackable package.

Integrated circuit package on package system

A method of manufacture of a package-on-package system includes: providing a package substrate; attaching a semiconductor die to the package substrate; forming an encapsulant around the semiconductor die to have a bottom exposed surface coplanar with a bottom surface of the package substrate and to have a top exposed surface with through openings extending therefrom through the bottom exposed surface; and creating through vias by applying solder into the through openings, the through vias coplanar with the bottom exposed surface of the encapsulant and coplanar with the top exposed surface of the encapsulant.

A method of manufacture of an integrated circuit packaging system includes: forming a substrate; mounting a base integrated circuit on the substrate; forming a leadframe interposer, over the base integrated circuit, by: providing a metal sheet, mounting an integrated circuit die on the metal sheet, injecting a molded package body on the integrated circuit die and the metal sheet, and forming a ball pad, a bond finger, or a combination thereof from the metal sheet that is not protected by the molded package body; coupling a circuit package on the ball pad; and forming a component package on the substrate, the base integrated circuit, and the leadframe interposer.

Integrated circuit packaging system with leadframe interposer and method of manufacture thereof

An integrated circuit package system includes: mounting an integrated circuit die over a carrier; attaching a delamination prevention structure over the integrated circuit die; and encapsulating the delamination prevention structure and the integrated circuit die.

Integrated circuit package system with delamination prevention structure

An integrated circuit packaging system includes: attaching a carrier, having a carrier top side and a carrier bottom side, and an interconnect without an active device attached to the carrier bottom side; and forming a first encapsulation, having a cavity, around the interconnect over the carrier top side with the interconnect partially exposed from the first encapsulation and with the carrier top side partially exposed with the cavity.

A method of manufacture of a package-on-package system includes: providing a package substrate; attaching a semiconductor die to the package substrate; forming an encapsulant around the semiconductor die to have a bottom exposed surface coplanar with a bottom surface of the package substrate and to have a top exposed surface with through openings extending therefrom through the bottom exposed surface; and creating through vias by applying solder into the through openings.

Growing community of inventors

Ichon-si, South Korea

DongSam Park