Intel Corporation

Dongming He

Sairam Agraharam

Carlton E Hanna

Vasudeva Atluri

Sujit Sharan

Debendra Mallik

Daoqiang Lu

Matthew Escobido

Chuan Hu

Bruce A Block

In one embodiment, the invention provides a method comprising fabricating a die bump on a die, the die bump being shaped and dimensioned to at least reduce the flow of solder material used, to attach the die bump to a package substrate, towards an under bump metallurgy (UBM) layer located below the die bump. Advantageously, the method may comprise performing a substrate reflow operation to attach the package substrate to the die bump, without performing a separate wafer reflow operation to reflow the die bump.

C4 joint reliability

A microelectronic die assembly. The die assembly includes a microelectronic die, and a thermally conductive element attached to the backside of the die with a thermal interface material. The thermally conductive element has lateral dimensions smaller than, substantially equal to, or larger than lateral dimensions of the die by up to a maximum amount, wherein the maximum amount is adapted to allow a mounting of the die assembly to a package substrate.

Microelectronic die assembly having thermally conductive element at a backside thereof and method of making same

Mechanical stresses are reduced between an electronic component having relatively low fracture toughness and a substrate having relatively greater fracture toughness. In an embodiment, the component may be a die having mounting contacts formed of a low yield strength material, such as solder. A package substrate has columnar lands formed of a relatively higher yield strength material, such as copper, having a relatively higher melting point than the component contacts and having a relatively high current-carrying capacity. The component contacts may be hemispherical in shape. The lands may be substantially cylinders, truncated cones or pyramids, inverted truncated cones or pyramids, or other columnar shapes. Methods of fabrication, as well as application of the package to an electronic assembly and to an electronic system, are also described.

Integrated circuit packages with reduced stress on die and associated methods

An apparatus and method for embedding a laser source on a semiconductor substrate and an optical interconnect to couple the laser source to internal components of the semiconductor substrate. An on-die waveguide is integrated on the semiconductor substrate. A package waveguide is disposed on the semiconductor substrate and evanescently coupled to the on-die waveguide. The laser source is embedded within the packaged waveguide to provide an optical signal to the on-die waveguide via the package waveguide.

Embedded on-die laser source and optical interconnect

Integrated circuit packages with reduced stress on die and associated substrates, assemblies, and systems

Growing community of inventors

Gilbert, AZ, United States of America

Dongming He