Samsung Electronics Co., Ltd.

Donghyun Roh

Sunki Min

Chaeho Na

Sangjin Hyun

Byung-Suk Jung

Guyoung Cho

Subin Shin

Sangkoo Kang

Sung Soo Kim

Sungsoo Kim

Dongsuk Shin

Pankwi Park

Koungmin Ryu

Gyuhwan Ahn

Chulwoong Lee

Woongsik Nam

Jaewon Lee

Jongmin Baek

Naein Lee

Sunghoon Cho

Iksoo Kim

Yoonkyong Lee

Muwoong Lee

Seokjin Chang

Sangmi Kim

Nae-in Lee

Wookyung You

Sunhye Lee

Kwangwon Ko

Sangshin Jang

Kyungsub Min

Seunggwang Kim

Yoonkyung Lee

A semiconductor device including a first conductive layer on a substrate, a second conductive layer on the first conductive layer, a contact structure between the first and second conductive layers, and a barrier structure surrounding a lower region of a side surface of the second conductive layer, wherein the contact structure includes a contact conductive layer having a first upper surface portion and a second upper surface extending from the first upper surface portion and being concave, and a gap-fill pattern fills a space between the second upper surface portion and the second conductive layer and includes a first gap-fill insulating layer including a metal element and a second gap-fill insulating layer including a silicon element, and the barrier structure includes a first etch stop layer and a barrier layer that include same materials as the first insulating material and the second insulating material, respectively, may be provided.

Semiconductor devices

A semiconductor device includes active fins extending in a first direction on a substrate; an isolation insulating layer covering a portion of side surfaces of the active fins; channel layers stacked vertically and spaced apart on the active fins; a gate pattern in a second direction across the active fins and the channel layers; and spacer layers across the active fins in the second direction on both sides of the gate pattern. At least one spacer layer extends downwardly along a side surface of the gate pattern such that a lower surface thereof contacts the isolation insulating layer. The lower surface of the spacer layer is higher than a level of upper surfaces of the active fins. The gate pattern has a lower surface contacting the isolation insulating layer. The lower surface of the gate pattern is lower than a level of the upper surfaces of the active fins.

Multi-bridge channel field effect transistor with multiple inner spacers

A method includes: forming a sacrificial gate structure on the active region; forming a spacer structure including a first spacer, a second spacer, and an air-gap spacer, the air-gap spacer capped by bending an upper portion of the second spacer toward an upper portion of the first spacer; forming an insulating structure on the sides of the spacer structure; forming a gap region; and forming a gate structure including a gate dielectric layer, a gate electrode, and a gate capping layer in the gap region. The upper portion of the second spacer is in physical contact with the upper portion of the first spacer on a contact surface, and a lowermost end of the contact surface is on a level higher than an upper surface of the gate electrode with the substrate being a reference base level.

Method of forming a semiconductor device with capped air-gap spacer

Disclosed is a method of extracting and using a semantic entity from a text message by an electronic device. The method includes: recognizing a text-based input; extracting a semantic entity from the text-based input; and providing the extracted semantic entity through an application in response to the application having a semantic setting that corresponds to the extracted semantic entity.

Electronic device and method for extracting and using semantic entity in text message of electronic device

An integrated circuit device includes: a fin-type active region on a substrate and including a fin top surface at a first level; a gate line on the fin-type active region; and an insulating structure on a sidewall of the fin-type active region. The insulating structure includes: a first insulating liner in contact with a sidewall of the fin-type active region; a second insulating liner on the first insulating liner and including an uppermost portion at a second level c than the first level; a lower buried insulating layer facing the sidewall of the fin-type active region and including a first top surface facing the gate line at a third level lower than the second level; and an upper buried insulating layer between the lower buried insulating layer and the gate line and including a second top surface at a fourth level equal to or higher than the second level.

Integrated circuit devices

A semiconductor device includes a gate structure including a gate electrode, a gate spacer layer on a side surface of the gate electrode, and a gate capping layer on the gate electrode. Moreover, the semiconductor device includes a source/drain region on at least one side of the gate structure, a contact plug on the source/drain region, and first and second insulating films between the contact plug and the gate structure and defining an air gap. The first insulating film includes a first surface, and a second surface extending from the first surface while forming a first angle. The second insulating film includes a third surface forming a second angle with the first surface of the first insulating film. The second angle is an acute angle narrower than the first angle. The air gap is defined by the first surface, the second surface, and the third surface.

A semiconductor device includes first and second active patterns on a substrate, the first and second active patterns adjacent to each other in a first direction with a first trench between the first and second active patterns, third and fourth active patterns on the substrate, the third and fourth active patterns adjacent to each other in the first direction with a second trench between the third and fourth active patterns. The semiconductor device includes a first device isolation layer in the first trench, and a second device isolation layer in the second trench. A width of the second trench in the first direction is greater than a width of the first trench in the first direction. The second device isolation layer includes a first protrusion and a second protrusion which protrude from a top surface of the second device isolation layer.

Method of manufacturing multi-channel field effect transistors

Disclosed is a semiconductor device comprising a substrate, a plurality of active patterns that protrude from the substrate, a device isolation layer between the active patterns, and a passivation layer that covers a top surface of the device isolation layer and exposes upper portions of the active patterns. The device isolation layer includes a plurality of first isolation parts adjacent to facing sidewalls of the active patterns, and a second isolation part between the first isolation parts. A top surface of the second isolation part is located at a lower level than that of top surfaces of the first isolation parts.

Semiconductor device

A method for manufacturing a semiconductor device includes forming a first active fin and a second active fin on a first active region and a second active region of a substrate, respectively, forming a device isolation layer to cover sidewalls of lower portions of the first active fin and the second active fin, forming a first liner layer and a second liner layer to cover upper portions of the first active fin and the second active fin, respectively, forming a first gate electrode and a second gate electrode on the first active fin and the second active fin, respectively, and forming a first source/drain region and a second source/drain region on the first active fin and the second active fin, respectively. The first liner layer includes a different material from a material of the second liner layer.

Semiconductor device and method of manufacturing the same

A semiconductor device includes first active patterns and second active patterns on a substrate, a first source/drain region on the first active patterns, a second source/drain region on the second active patterns and a device isolation layer filling a first trench between adjacent ones of the first active patterns and a second trench between adjacent ones of the second active patterns. A liner layer is disposed on the device isolation layer between the adjacent ones of the second active patterns. The device isolation layer between the adjacent ones of the first active patterns has a recess therein under the first source/drain region and a bottom surface of the liner layer between the adjacent ones of the second active patterns is higher than the recess.

Growing community of inventors

Suwon-si, South Korea

Donghyun Roh