Samsung Electronics Co., Ltd.

Donghyuk Yeom

Seonghwa Park

Kwan Heum Lee

Sechan Lim

Kwanheum Lee

Junkyum Kim

Sohyun Seo

A semiconductor device may include first and second active regions on a substrate, first and second insulating structures on the first and second active regions, respectively, vertically stacked channel layers on each of the first and second insulating structures, first and second gate structures intersecting the first and second active regions, respectively, and surrounding the channel layers, first and second source/drain regions doped with different conductivity-type impurities, the first and second source/drain regions being on sides of the first and second gate structures, respectively, and contacting the channel layers, and at least a portion of each of the first and second insulating structures extending upwardly along a side surface of a corresponding one of the first and second source/drain regions.

Semiconductor device

Disclosed are a semiconductor device and a method of fabricating the same. The semiconductor device includes an active pattern on a substrate, a device isolation layer provided on the substrate to define the active pattern, a pair of source/drain patterns on the active pattern and a channel pattern therebetween, the channel pattern including semiconductor patterns which are stacked and are spaced apart from each other, a gate electrode crossing the channel pattern, and a gate spacer on a side surface of the gate electrode. The gate spacer located on the device isolation layer includes an upper portion with a first thickness and a lower portion with a second thickness. The second thickness is larger than the first thickness, and the lower portion of the gate spacer is located at a level lower than the uppermost one of the semiconductor patterns.

Semiconductor device and method of fabricating the same

A semiconductor device includes; an active pattern on a substrate, a source/drain pattern on the active pattern, a channel pattern connected to the source/drain pattern and including semiconductor patterns spaced apart in a vertical stack, and a gate electrode extending across the channel pattern. The semiconductor patterns includes a first semiconductor pattern and a second semiconductor pattern. The gate electrode includes a first part between the substrate and the first semiconductor pattern and a second part between the first semiconductor pattern and the second semiconductor pattern. A width of the first part varies with a depth of the first part, such that a width of a middle portion of the first part is less than a width of a lower portion of the first part and a width of an upper portion of the first part.

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Seoul, South Korea

Donghyuk Yeom