Dongbu Electronics, Co. Ltd.

Other

Dongbu Hitek Co., Ltd.

Dong Yeal Keum

Chang Hun Han

Cheol Soo Park

Chee Hong Choi

Disclosed is a method for fabricating a semiconductor device. The method can include forming a first barrier pattern to cover a first region of a semiconductor substrate while exposing second and third regions of the semiconductor substrate, forming a first oxide layer pattern on the second and third regions, forming a second barrier pattern to cover the third region while exposing the first and second regions, forming a second oxide layer pattern on the first and second regions, forming a third oxide layer pattern on the second region by removing the second and first oxide layer patterns formed on the first and third regions, forming a silicide metal layer on the first, second, and third regions, and selectively forming silicide on the first and third regions by performing an annealing process with respect to the silicide metal layer.

Method for fabricating silicide layers for semiconductor device

A capacitor structure and a method of fabricating the capacitor structure wherein. The lower electrode and the upper electrode are constructed to be separated from each other by a predetermined interval and to be engaged with each other using a series of alternating ridges so that an effective surface area can increase within a limited area.

Capacitor and method for fabricating the same

Methods for fabricating a copper interconnect are disclosed. A disclosed method comprises: employing a damascene process to form a first trench in a first insulating layer; depositing a first barrier layer and a first copper layer on the first insulating layer; forming a bottom copper interconnect by planarizing the first copper layer; depositing and planarizing a second barrier layer; depositing a second insulating layer; forming a via hole in the second insulating layer; employing a damascene process to form a second trench in the second insulating layer; and forming a via and an upper copper interconnect by depositing a third barrier layer and a second copper layer on the second insulating layer.

Methods for fabricating a copper interconnect

Methods of fabricating semiconductor devices are disclosed. One example method includes forming a gate oxide and a gate electrode on a semiconductor substrate; performing a first ion implantation process for the formation of an LDD (lightly doped drain) region in the substrate; forming spacers on the sidewalls of the gate electrode; performing a second ion implantation process for the formation of a junction region in the substrate using the spacers as mask; forming a trench for device isolation by removing selectively the top portion of the substrate between the spacers; forming a sidewall oxide layer on the resulting substrate; forming a diffusion barrier on the sidewall oxide layer; depositing a gap filling insulation layer over the diffusion barrier; planarizing the gap filling insulating layer; and removing selectively some part of the gap filling insulation layer to form contact holes.

Methods of fabricating semiconductor devices

A method for fabricating a dynamic random access memory capacitor. It is characterized by forming multi-insulating films with different etch selection ratio between conduction layers over a planarizing film, making the upper and lower portion of conduction pattern undercut by use of the difference in etch selection ratio when defining the capacitor into a pin structure, forming the insulating spacer in such a way to fill the undercut portions, forming the conduction spacer at the side wall of the insulating spacer, and etching the conduction layer at the inside of the insulating spacer, in a predetermined thickness, to form the inside conduction spacer. Accordingly, the capacitor fabricated by the method is structured to have a plurality of pin-shaped conduction layers with each being coated with a conduction spacer. Since the method takes advantage of the difference in etch selection ratio, it employs few etch masks, which facilitates the fabrication of DRAM capacitor. In addition, the increase of surface area by the conduction spacers results in the increase of capacitance in the capacitor. Furthermore, the capacitor has fewer steps than the conventional ones with the same capacitance, so that the method has significant advantage over conventional methods, including the capability of coating the steps.

Growing community of inventors

Icheon-si, South Korea

Dong Yeal Keum