Samsung Electronics Co., Ltd.

Hynix Semiconductor Inc.

Skhynix Inc.

Korea University Industrial Academic Collaboration Foundation

Dong-Suk Shin

Hoi-Sung Chung

Nae-in Lee

Pan-Kwi Park

Hwa-Sung Rhee

Myung-Sun Kim

Ho Young Lee

Yong-Kuk Jeong

Tetsuji Ueno

Gi-Gwan Park

Seung-hwan Lee

Dong-Woo Kim

Dong-Hyun Roh

Seung-Hwan Lee

Hyun-Woo Lee

Hong-Jae Shin

Ho Joong Lee

Tae-Gyun Kim

Sung-young Lee

Ha-Jin Lim

Jeong-yun Lee

Kwan-heum Lee

Won-Joo Yun

Hyung-jun Lim

Jae-hong Park

Kyoung-Mook Lim

Hyun-Kwan Yu

Tae-young Kim

Ki-chul Kim

Hyung-Dong Lee

Chul Woo Kim

Jin-bum Kim

Min-Hee Choi

Yang Xu

Dong-woo Kim

Su-Jin Jung

Hyun-Jun Sim

Cho-eun Lee

Sung-Min Kim

Seok-Jun Won

Cheol-Woo Park

Jae-Hong Park

Dong-won Kim

Tae-Hee Lee

Weon-hong Kim

Han-jin Lim

Jae-Gon Lee

Seung-hun Lee

Ho Won Lee

Dong-Hyuk Kim

Young-Tak Kim

Chul-Woong Lee

Geo-Myung Shin

Dong-Chan Suh

Yeong-Jong Jeong

Si-Hyung Lee

Hyun-Chul Kang

Seong-Jin Nam

Heo-jin Byeon

Sung-Cheol Park

Andrew-Tae Kim

Ho-Sung Son

Ueno Tetsuji

Kook-tae Kim

Myung-gil Kang

Yong-Joo Lee

Sung-Uk Jang

Kang-Hun Moon

Hyun-ho Noh

Ju-Ri Lee

Jung-Shik Heo

Gi-gwan Park

Andrew-tae Kim

Hyun Soo Chae

Chulwoo Kim

Yong-seung Kim

Seo-Jin Jeong

Yu-yeong Jo

Ryong Ha

Joo-won Lee

Seh-woong Jeong

Tae-gyun Kim

Ki-eun Kim

Hion-suck Baik

Tae-Sun Kim

Ji-Yong Ahn

Shi Li Quan

Andrew Tae Kim

Jun-Jung Kim

Ja-Beom Koo

Sung-uk Jang

Jung-Deog Lee

Il-young Yoon

Kyung-Mook Lim

Jang-Hyeon Lee

Shi Ii Quan

Joo-Won Lee

Inhwa Jung

Young-Jung Choi

In-Hwa Jung

A semiconductor device includes a substrate including a first region and a second region, fin type active areas extending in a first direction away from the substrate in each of the first and second regions, a plurality of nanosheets extending parallel to an upper surface of the fin type active areas and being spaced apart from the upper surface of the fin type active areas, a gate extending over the fin type active areas in a second direction crossing the first direction, a gate dielectric layer interposed between the gate and each of the nanosheets, first source and drain regions included in the first region and second source and drain regions included in the second region, and insulating spacers interposed between the fin type active areas and the nanosheets, wherein air spacers are interposed between the insulating spacers and the first source and drain regions.

Semiconductor device including source/drain having sidewalls with convex and concave portions

A semiconductor device may include a first active fin, a second active fin and a gate structure. The first active fin may extend in a first direction on a substrate and may include a first straight line extension portion, a second straight line extension portion, and a bent portion between the first and second straight line extension portions. The second active fin may extend in the first direction on the substrate. The gate structure may extend in a second direction perpendicular to the first direction on the substrate. The gate structure may cross one of the first and second straight line extension portions of the first active fin and may cross the second active fin.

Semiconductor devices with bent portions

Multi-gate metal-oxide-semiconductor field effect transistor

A semiconductor device may include a first active fin, a plurality of second active fins, a first source/drain layer structure, and a second source/drain layer structure. The first active fin may be on a first region of a substrate. The second active fins may be on a second region of the substrate. The first and second gate structures may be on the first and second active fins, respectively. The first source/drain layer structure may be on a portion of the first active fin that is adjacent to the first gate structure. The second source/drain layer structure may commonly contact upper surfaces of the second active fins adjacent to the second gate structure. A top surface of the second source/drain layer structure may be further from the surface of the substrate than a top surface of the first source/drain layer structure is to the surface of the substrate.

Semiconductor devices with layers commonly contacting fins and methods of manufacturing the same

Methods for fabricating semiconductor devices include forming a fin-type pattern protruding on a substrate, forming a gate electrode intersecting the fin-type pattern, forming a first recess adjacent to the gate electrode and within the fin-type pattern by using dry etching, forming a second recess by treating a surface of the first recess with a surface treatment process including a deposit process and an etch process, and forming an epitaxial pattern in the second recess.

Method of fabricating semiconductor device

Semiconductor device

Provided is a semiconductor device including: a fin structure on a substrate including a negative channel field-effect transistor (nFET) region and a positive channel field-effect transistor (pFET) region; a gate structure on the fin structure; and a source/drain structure adjacent to the gate structure, wherein the source/drain structure formed in the nFET region is an epitaxial layer including an n-type impurity at a concentration of about 1.8&#xd7;10/cmor more, includes silicon (Si) and germanium (Ge) on an outer portion of the source/drain structure, and includes Si but not Ge in an inner portion of the source/drain structure, wherein an inclined surface contacting an uppermost surface of the source/drain structure forms an angle of less than about 54.7&#xb0; with a top surface of the fin structure.

Semiconductor device having a fin structure and a manufacturing method thereof

A dummy gate electrode layer and a dummy gate mask layer may be formed on a substrate. The dummy gate mask layer may be patterned to form a dummy gate mask so that a portion of the dummy gate electrode layer is exposed. Ions may be implanted into the exposed portion of the dummy gate electrode layer and a portion of the dummy gate electrode layer adjacent thereto by an angled ion implantation to form a growth blocking layer in the dummy gate electrode layer. The dummy gate electrode layer may be etched using the dummy gate mask as an etching mask to form a dummy gate electrode. A spacer may be formed on side surfaces of a dummy gate structure including the dummy gate electrode and the dummy gate mask. An SEG process may be performed to form an epitaxial layer.

Semiconductor devices and methods of manufacturing the same

Multigate metal-oxide semiconductor field effect transistor

In a semiconductor device, a first active region has a first &#x3a3;-shape, and the second active region has a second &#x3a3;-shape. When a line that is perpendicular to the substrate and passes a side surface of a first gate electrode in the first region is defined as a first vertical line, when a line that is perpendicular to the substrate and passes a side surface of a second gate electrode in the second region is defined as a second vertical line, when a shortest distance between the first vertical line and the first trench is defined as a first horizontal distance, and when a shortest distance between the second vertical line and the second trench is defined as a second horizontal distance, a difference between the first horizontal distance and the second horizontal distance is equal to or less than 1 nm.

Semiconductor device having embedded strain-inducing pattern and method of forming the same

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Yongin-si, South Korea

Dong-Suk Shin