Samsung Electronics Co., Ltd.

Dong-Seog Eun

Sung-Nam Chang

Jung-Dal Choi

Kyu-Charn Park

Sung-Hun Lee

Tae-Kyung Kim

Dong-Won Chang

Seung-Gun Seo

A method of forming a semiconductor device, where the method may include forming a first trench in a semiconductor substrate, forming first device isolation patterns that fill the first trench, forming spacers on sidewalls of the first device isolation patterns, forming a second trench in the semiconductor substrate between first device isolation patterns, and forming second device isolation patterns that fill the second trench. The second trench is formed using an etching process adopting the first device isolation pattern and the spacer as a mask.

Method of forming semiconductor device

Provided is a nonvolatile memory device and a method of forming the nonvolatile memory device. The nonvolatile memory device includes a floating gate formed on a first active region doped with a first-conductivity-type dopant. The floating gate is doped with the first-conductivity-type dopant. Therefore, the thickness of a tunnel insulation layer can be kept thin, and the threshold voltage of a nonvolatile memory cell including the floating gate can be increased. As a result, the endurance of the tunnel insulation layer and the data retention characteristics of the nonvolatile memory cell is improved.

Nonvolatile memory device and method of forming the same

Methods of forming an integrated circuit device include forming first and second device isolation regions at side-by-side locations within a semiconductor substrate to thereby define a semiconductor active region therebetween. These first and second device isolation regions have sidewalls that extend vertically relative to the semiconductor active region. A first gate insulating layer is formed on a surface of the semiconductor active region. A central portion of the first gate insulating layer extending opposite the semiconductor active region is thinned to thereby define gate insulating residues extending adjacent sidewalls of the first and second device isolation regions. A second gate insulating layer is formed on the gate insulating residues to thereby yield a non-uniformly thick third gate insulating layer. A gate electrode is formed on the non-uniformly thick third gate insulating layer.

Methods of forming integrated circuit devices having gate electrodes formed on non-uniformly thick gate insulating layers

A method of fabricating a flash memory device produces a device that has a small cell area and yet a high coupling ratio. First, a basic structure is provided that includes a substrate, a field isolation film protruding from the substrate, and floating gates disposed on the substrate on opposite sides of the floating gate. A first etch process is performed to remove a portion of the field isolation film and thereby expose upper portions of the floating gates. Then, a second etch process is performed to knock off the edges of the floating gates. Thus, a large amount of space is secured between the floating gates for a dielectric film and a control gate.

Flash memory and method of fabricating the same

A shallow trench isolation type semiconductor device includes a gate insulating layer formed in a first region and in a second region. The gate insulating layer is of greater thickness in the first region, relative to the thickness of the gate insulating layer in the second region. A shallow trench isolation layer is also formed in the first region and the second region, the shallow trench isolation layer in the first region being thinner than shallow trench isolation layer in the second region.

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Seoul, South Korea

Dong-Seog Eun