Samsung Electronics Co., Ltd.

Dong-Chan Lim

Ju-Il Choi

Kwang-Jin Moon

Hee-Sook Park

Byung-Hak Lee

Gil-heyun Choi

Tae-Seong Kim

Atsushi Fujisaki

Jae-Hwa Park

Chang-Won Lee

Woong-Hee Sohn

Kwangjin Moon

Sun-Pil Youn

Jang-Hee Lee

Ju-Bin Seo

Su-Jeong Park

Jin Ho An

Jong-Ryeol Yoo

JuBin Seo

Sujeong Park

Hak-seung Lee

Dae-suk Lee

Wandon Kim

Hyunbae Lee

Donggon Yoo

Sunyoung Noh

Byung-Hee Kim

In-Soo Jung

Jinnam Kim

Byeong-Yun Nam

Hakseung Lee

Ho-Jin Lee

Gil-Heyun Choi

Tae-Ho Cha

Geum-Jung Seong

Soo-Ik Jang

Sun-Pil Yun

Dae-Suk Lee

Disclosed is a semiconductor device including a conductive pattern on a substrate, a passivation layer on the substrate and including an opening that partially exposes the conductive pattern, and a pad structure in the opening of the passivation layer and connected to the conductive pattern. The pad structure includes a first metal layer that fills the opening of the passivation layer and has a width greater than that of the opening, and a second metal layer on the first metal layer. The first metal layer has a first thickness at an outer wall of the first metal layer, a second thickness on a top surface of the passivation layer, and a third thickness on a top surface of the conductive pattern. The second thickness is greater than the first thickness, and the third thickness is greater than the second thickness.

Semiconductor device

A semiconductor device includes an interlayer dielectric layer on a substrate, a first connection line that fills a first trench of the interlayer dielectric layer, the first trench having a first width, and a second connection line that fills a second trench of the interlayer dielectric layer, the second trench having a second width greater than the first width, and the second connection line including a first metal layer that covers an inner sidewall of the second trench, a barrier layer that covers a bottom surface of the second trench, and a second metal layer on the first metal layer and the barrier layer, the first connection line and the first metal layer include a first metal, and the second metal layer includes a second metal different from the first metal.

A semiconductor package includes a first semiconductor chip and a second semiconductor chip stacked on the first semiconductor chip. The first semiconductor chip includes a substrate having a first via hole, an insulation interlayer formed on the substrate and having a first bonding pad in an outer surface thereof and a second via hole connected to the first via hole and exposing the first bonding pad, and a plug structure formed within the first and second via holes to be connected to the first bonding pad. The second semiconductor chip includes a second bonding pad bonded to the plug structure which is exposed from a surface of the substrate of the first semiconductor chip.

Semiconductor device, semiconductor package and method of manufacturing the same

A bevel etching apparatus includes a chuck plate that is configured to receive a substrate, a lower ring surrounding a circumference of the chuck plate, a cover plate on the chuck plate, and an upper ring surrounding a circumference of the cover plate. The lower ring includes a ring base and a protrusion that extends upwardly from an edge of the ring base and surrounds a lower portion of a sidewall of the substrate.

Apparatus for etching substrate bevel and semiconductor fabrication method using the same

A semiconductor device is provided. The semiconductor device includes a first insulating interlayer disposed on a first surface of a substrate; a pad pattern disposed on a lower surface of the first insulating interlayer, the pad pattern including a first copper pattern; and a through silicon via passing through the substrate and the first insulating interlayer, and contacting the first copper pattern of the pad pattern. The through silicon via includes a first portion passing through the substrate and the first insulating interlayer, and a second portion under the first portion and extending to a portion of the first copper pattern in the pad pattern. A boundary of the through silicon via has a bent portion between the first portion and the second portion.

Semiconductor device having a through silicon via and methods of manufacturing the same

An integrated circuit device includes a substrate, a landing pad on the substrate, and a through-via structure passing through the substrate and connected to the landing pad. The through-via structure may include a conductive plug, a first conductive barrier layer covering a sidewall and a lower surface of the conductive plug, and a second conductive barrier layer covering a sidewall of the first conductive barrier layer.

Integrated circuit device and method of manufacturing the same

Semiconductor chips and methods of manufacturing the same are provided. The semiconductor chip includes a substrate, an interlayer insulation layer including a bottom interlayer insulation layer on an upper surface of the substrate and a top interlayer insulation layer on the bottom interlayer insulation layer, an etch stop layer between the bottom interlayer insulation layer and the top interlayer insulation layer, a landing pad on the interlayer insulation layer, and a through via connected to the landing pad through the substrate, the interlayer insulation layer, and the etch stop layer. The etch stop layer is isolated from direct contact with the landing pad.

Semiconductor chips and methods of manufacturing the same

In an ohmic layer and methods of forming the ohmic layer, a gate structure including the ohmic layer and a metal wiring having the ohmic layer, the ohmic layer is formed using tungsten silicide that includes tungsten and silicon with an atomic ratio within a range of about 1:5 to about 1:15. The tungsten silicide may be obtained in a chamber using a reaction gas including a tungsten source gas and a silicon source gas by a partial pressure ratio within a range of about 1.0:25.0 to about 1.0:160.0. The reaction gas may have a partial pressure within a range of about 2.05 percent to about 30.0 percent of a total internal pressure of the chamber. When the ohmic layer is employed for a conductive structure, such as a gate structure or a metal wiring, the conductive structure may have a reduced resistance.

Semiconductor device including an ohmic layer

A method of forming a semiconductor device can include forming a trench in a semiconductor substrate to define an active region. The trench is filled with a first device isolation layer. A portion of the first device isolation layer is etched to recess a top surface of the first device isolation layer below an adjacent top surface of the active region of the semiconductor substrate and to partially expose a sidewall of the active region. The exposed sidewall of the active region is epitaxially grown to form an extension portion of the active region that extends partially across the top surface of the first device isolation layer in the trench. A second device isolation layer is formed on the recessed first device isolation layer in the trench. The second device isolation layer is etched to expose a top surface of the extension portion of the active region and leave a portion of the second device isolation layer between extension portions of active regions on opposite sides of the trench. An interlayer dielectric is formed on the semiconductor substrate and the second device isolation layer. A conductive contact is formed extending through the interlayer dielectric layer and directly contacting at least a portion of both the active region and the extension portion of the active region overlying the second device isolation layer.

Methods of forming semiconductor devices with extended active regions

Growing community of inventors

Hwaseong-si, South Korea

Dong-Chan Lim