International Business Machines Corporation

Donato Orazio Forlenza

Orazio Pasquale Forlenza

Phong T Tran

Bryan J Robbins

William James Hurley

Todd Michael Burdine

Franco Motika

Phillip J Nigh

Joseph E Eckelman

Michael P Grace

Adrian C Anderson

Edward Emile Kelley

Norman J Dauerer

Thomas J Knips

Gary William Maier

Robert Benjamin Gass

John James Shushereba

Steven Michnowski

James Bernard Webb

Adrian Charles Anderson

Franco Molika

A method, system, and computer program product to test a semiconductor device are described. The system includes an input interface to receive a set of test patterns to test the semiconductor device and a user selection corresponding to a subset of the set of test patterns. The system also includes a processor to process the subset of the set of test patterns to output test data to the semiconductor device.

Selective test pattern processor

A method, system, and computer program product to test a semiconductor device are described. The method includes receiving a set of test patterns for testing the semiconductor device and a user selecting a subset of the set of test patterns. The method also includes cataloging a content of pattern files associated with the subset of the set of test patterns to generate a catalog, and processing the catalog to output test data to the semiconductor device.

A method of performing root cause identification for a failure on an integrated circuit with a logic built-in self-test (LBIST) system and an LBIST system to perform root cause identification are described. The system includes one or more channel scan paths, each of the one or more macros associated with each of the one or more channel scan paths being executed during a test cycle, and a processor to initiate one or more of the test cycles via an LBIST controller, identify a failing test cycle among the one or more of the test cycles, identify a failing channel scan path among the one or more channel scan paths for the failing cycle, identify the one or more macros associated with the failing channel scan path, and iteratively check each of the one or more macros associated with the failing channel scan path to perform the root cause identification.

Logic-built-in-self-test diagnostic method for root cause identification

A method of performing root cause identification for a failure on an integrated circuit with a logic built-in self-test (LBIST) system and an LBIST system to perform root cause identification are described. The method includes completing one or more cycles of test with the LBIST system, each of the one or more cycles implementing one or more macros associated with each of one or more channel scan paths. The method also includes identifying, using a processor, a failing cycle among the one or more cycles of test, identifying a failing channel scan path among the one or more channel scan paths associated with the failing cycle, and identifying the one or more macros associated with the failing channel scan path. The method further includes iteratively checking each of the one or more macros associated with the failing channel scan path to perform the root cause identification.

A method, apparatus and computer program product are provided for implementing diagnostics of transitional scan chain defects using structural Logic Built In Self Test (LBIST) test patterns. A LBIST test pattern is applied to the device under test and multiple system clock sequences with variable loop control are applied in a passing operating region and scan data is unloaded. The LBIST test pattern is applied to the device under test and multiple system clock sequences with variable loop control are applied in a failing operating region for the device under test and scan data is unloaded. Then the unload data from the passing operating region and the failing operating region are compared. The identified latches having different results are identified as potential AC defective latches. The identified potential AC defective latches are sent to a Physical Failure Analysis system.

Implementing diagnosis of transitional scan chain defects using logic built in self test LBIST test patterns

A method, apparatus and computer program product are provided for implementing isolation of VLSI AC scan chain defects using structural Array Built In Self Test (ABIST) test patterns. An ABIST test pattern is applied to the device under test and multiple ABIST array algorithms are applied in a passing operating region and each scan chain is unloaded. The ABIST test pattern is applied to the device under test and multiple ABIST array algorithms are applied in a failing operating region for the device under test. Then the unload data from the passing operating region and the failing operating region are compared. The identified latches having different results are identified as potential AC defective latches. The identified potential AC defective latches are sent to a Physical Failure Analysis system.

Implementing isolation of VLSI scan chain using ABIST test patterns

A method for performing a logical built-in self-test of an integrated circuit is disclosed. The method includes performing a flush and scan test to determine whether the scan chains function correctly. If one of the scan chains does not function correctly, the logical built-in self-test is terminated. If each of the scan chains functions correctly, a structural test of the design-for-test logic supporting LBIST is performed to determine whether the LBIST design-for-test logic functions correctly. If the LBIST design-for-test logic does not function correctly, the logical built-in self-test is terminated. If the LBIST design-for-test logic functions correctly, a level sensitive scan design test of the functional combinational logic is performed using the logic supporting LBIST design-for-test to determine if the integrated circuit functions correctly.

Method and apparatus for performing logic built-in self-testing of an integrated circuit

A method for implementing at speed bit fail mapping of an embedded memory system having ABIST (Array Built In Self Testing), comprises using a high speed multiplied clock which is a multiple of an external clock of an external tester to sequence ABIST bit fail testing of the embedded memory system. Collect store fail data during ABIST testing of the embedded memory system. Perform a predetermined number of ABIST runs before issuing a bypass order substituting the external clock for the high speed multiplied clock. Use the external clock of the tester to read bit fail data out to the external tester.

AC ABIST diagnostic method, apparatus and program product

A method, system and computer program product for testing the Design-For-Testability/Design-For-Diagnostics (DFT/DFD) and supporting BIST functions of a custom microcode array. Upon completion of the LSSD Flush and Scan tests, the ABIST program is applied to target the logic associated direct current (DC) and alternating current (AC) faults of ABIST array Design-For-Testability/Design-For-Diagnostics DFT/DFD functions that support the microcode array. A LSSD test of the DFT functional combinational logic is performed by applying generated LSSD deterministic test patterns targeting the ABIST design-for-test faults to determine if the DFT supporting the microcode array is functioning correctly. Additional tests may be terminated upon resulting failure of the applied ABIST DFT circuitry surrounding the arrays.

Verification of array built-in self-test (ABIST) design-for-test/design-for-diagnostics (DFT/DFD)

This invention involves the use of the JTAG functional test patterns and exercisors to solve the problem of diagnosing broken scan chains in either a serial or a lateral broadside insertion manner across all latch system ports and to analyze the response data efficiently for the purpose of readily identifying switching and non-switching latches with the next to last non-switching latch being the point of the break within a defective scan chain(s). This comprehensive latch perturbation, in conjunction with iterative diagnostic algorithms is used to identify and to pinpoint the defective location in such a broken scan chain(s). This JTAG Functional test function and the JTAG test patterns ultimately derived therefrom, can take on different forms and origins, some external to a product and some internal to a product.

Automated system and processing for expedient diagnosis of broken shift registers latch chains

A method of diagnosing semiconductor device functional testing failures by combining deterministic and functional testing to create a new test pattern based on functional failure by determining the location of the type of error in the failing circuit. This is accomplished by identifying the failing vector during the functional test, observing the states of the failed device by unloading the values of the latches from the LSSD scan chain before the failing vector, generating a LOAD from the unloaded states of the latches, applying the generated LOAD as the first event of a newly created independent LSSD deterministic pattern, applying the primary inputs and Clocks that produced the failure to a correctly operating device, unloading the output of the correctly operating device to generate a deterministic LSSD pattern; and applying the generated deterministic LSSD pattern to the failing device to diagnose the failure using existing LSSD deterministic tools.

Functional pattern logic diagnostic method

A method, apparatus and computer program product are provided for implementing deterministic based broken scan chain diagnostics. A deterministic test pattern is generated and is loaded into each scan chain in the device under test using lateral insertion via system data ports applying system clocks. Then each scan chain is unloaded and a last switching latch is identified. The testing steps are repeated a selected number of times. Then checking for consistent results is performed. When consistent results are identified, then the identified last switching latch is sent to a Physical Failure Analysis system.

implementing deterministic based broken scan chain diagnostics

Method for implementing deterministic based broken scan chain diagnostics

A method, apparatus and computer program product are provided implementing a scan chain diagnostics technique. The diagnostics technique includes employing fuses coupled to latches of the scan chain to load a known logic value into the latches at known locations of the scan chain, and then unloading values from the scan chain, and if the scan chain is defective (for example, based on the unloaded logic values), then localizing a defect in the scan chain from the unloaded logic values by comparison thereof with the known locations of the latches of the scan chain loaded with the known logic value via the fuses. The scan chain may be predesigned with fuses spaced periodically across the chain every n latches to facilitate subsequent localization of a detected defect in the scan chain.

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Donato Orazio Forlenza