International Business Machines Corporation

Donald W Brouillette

Ronald Lee Mendelson

Timothy Charles Krywanczyk

Thomas George Ference

Eric Gerhard Liniger

Robert F Cook

Matthew R Whalen

Joseph D Danaher

Wayne John Howell

Michael Straight Hibbs

Harold G Linde

Jerome Brett Lasky

Rick L Mohler

John M Blondin

Amye L Wells

Allan D Abrams

Steven A Martel

Wolfgang Otto Rauscher

David Frederick Diefenderfer

Rene A Lamothe

Ivan J Stone

There is provided a UV energy curable tape comprising an adhesive material including a UV energy curable oligomer, a UV energy initiator, and a material which emits optical light when the tape composition is substantially fully cured. A semiconductor chip made using the tape is also provided.

Ultraviolet energy curable tape and method of making a semiconductor chip using the tape

There is provided a method for making a wafer comprising the steps of providing a substrate having a first surface, an opposite second surface, and at least one side edge defining a thickness of the substrate, the at least one side edge having a first peripheral region and a second peripheral region adjacent to the first peripheral region. The method includes applying a fluid to the first surface and the first peripheral region of the at least one side edge and removing the opposite second surface and the second peripheral region of the at least one side edge to form a third surface. A semiconductor chip made from the method for making the wafer is also provided.

Semiconductor wafer front side protection

A method and apparatus for controlling the thickness of a semiconductor wafer during a backside grinding process are disclosed. The present invention uses optical measurement of the wafer thickness during a backside grinding process to determine the endpoint of the grinding process. Preferred methods entail measuring light transmitted through or reflected by a semiconductor wafer as a function of angle of incidence or of wavelength. This information is then used, through the use of curve fitting techniques or formulas, to determine the thickness of the semiconductor wafer. Furthermore, the present invention may be used to determine if wedging of the semiconductor occurs and, if wedging does occur, to provide leveling information to the thinning apparatus such that a grinding surface can be adjusted to reduce or eliminate wedging.

Wafer thickness control during backside grind

A structure and method of formation. The substrate has front and back surfaces on opposite sides of the substrate. The substrate has a backside portion extending from the back surface to a second depth into the substrate as measured from the front surface. At least one via is formed in the substrate and extends from the front surface to a via depth into the substrate. The via depth is specific to each via. The via depth of each via is less than an initial thickness of the substrate. The second depth does not exceed the minimum via depth of the via depths. Organic material (e.g., photoresist) is inserted into each via. The organic material is subsequently covered with a tape, followed by removal of the backside portion of the substrate. The tape is subsequently removed from the organic material, followed by removal of the organic material from each via.

Use of photoresist in substrate vias during backside grind

There is provided a method for making a wafer including the steps of providing a substrate having a first surface, an opposite second surface, and at least one side edge defining a thickness of the substrate, the at least one side edge having a first peripheral region and a second peripheral region adjacent to the first peripheral region. The method includes applying a fluid to the first surface and the first peripheral region of the at least one side edge and removing the opposite second surface and the second peripheral region of the at least one side edge to form a third surface. A semiconductor chip made from the method for making the wafer is also provided.

A method and system for dicing a semiconductor wafer providing a structure with greatly reduced backside chipping and cracking, as well as increased die strength. Semiconductor chip structures obtained from wafers diced according to this invention are also encompassed.

Method and system for dicing wafers, and semiconductor structures incorporating the products thereof

A semiconductor structure with greatly reduced backside chipping and cracking, as well as increased die strength, accommodation of compact assembly with a carrier such as another semiconductor chip, and resistance to package damage is provided by dicing chips from a wafer in a manner that chamfers edges of the chips. Similar advantages are obtained in multi-chip structure.

Semiconductor structure and package including a chip having chamfered edges

A method of providing a predetermined level and state of stress in a film deposited on a surface of a substrate. In one embodiment, a layer of crystalline material is deposited on a surface of a substrate and then a layer of amorphous material is deposited on the layer of crystalline material. Then, the layers are heated, causing the amorphous material to crystallize. Such crystallization reduces, or even changes the state of, stress in the amorphous layer, which in turn alters the forces applied by the layer to adjacent regions of the substrate. The method may be used for filling a deep-trench capacitor of the type used in trench-storage DRAMs.

Method of controlling stress in a film

A method is described by which the mechanical strength of chips of semiconductor devices can be controlled by appropriate wafer finishing and sorted by knowledge of the finishing method and chip and wafer geometry. The control and sorting derive from a knowledge of the geometry of the striations remaining on the back of chips after the wafer-grinding finishing step.

Method and apparatus for preventing chip breakage during semiconductor manufacturing using wafer grinding striation information

A method for manufacturing a low profile semiconductor chip, includes fabricating a semiconductor device on a semiconductor wafer, grinding, with a grinding tool, a backside of the semiconductor wafer to reduce a thickness thereof, and with the wafer in the grinding tool, providing a support structure on the ground backside of the wafer.

Growing community of inventors

St. Albans, VT, United States of America

Donald W Brouillette