Micron Technology Incorporated

Other

Donald L Yates

Garry Anthony Mercaldi

Max F Hineman

Kevin J Torek

Joel A Drewes

Donald L Westmoreland

James J Hofmann

Karen T Signorini

Li Li

Janos Fucsko

Gundu M Sabde

Prashant Raghu

Robert J Hanson

Niraj B Rana

Sandra Tagg

Patrick M Flynn

Kyle Grant

Paul A Morgan

Some embodiments include methods of treating semiconductor substrates. The substrates may be exposed to one or more conditions that vary continuously. The conditions may include temperature gradients, concentration gradients of one or more compositions that quench etchant, pH gradients to assist in removing particles, and/or concentration gradients of one or more compositions that assist in removing particles. The continuously varying conditions may be imparted by placing the semiconductor substrates in a bath of flowing rinsing solution, with the bath having at least two feed lines that provide the rinsing solution therein. One of the feed lines may be at a first condition, and the other may be at a second condition that is different from the first condition. The relative amount of rinsing solution provided to the bath by each feed line may be varied to continuously vary the condition within the bath.

Methods of treating semiconductor substrates, methods of forming openings during semiconductor fabrication, and methods of removing particles from over semiconductor substrates

An improved composition and method for cleaning a surface of a semiconductor wafer are provided. The composition can be used to selectively remove a low-k dielectric material such as silicon dioxide, a photoresist layer overlying a low-k dielectric layer, or both layers from the surface of the wafer. The composition is formulated according to the invention to provide a desired removal rate of the low-k dielectric and/or photoresist from the surface of the wafer. By varying a fluorine ion component, and the amounts of the fluorine ion component and an acid component, and controlling the pH, a composition can be formulated in order to achieve a desired low-k dielectric removal rate that ranges from slow and controlled at about 50 to about 1000 angstroms per minute, to a relatively rapid removal of low-k dielectric material at greater than about 1000 angstroms per minute. The composition can also be formulated to selectively remove the photoresist layer, leaving the underlying low-k dielectric layer essentially intact.

Compositions for use in semiconductor devices

The present invention provides a method of fabricating a portion of a memory cell, the method comprising providing a first conductor in a trench which is provided in an insulating layer and flattening an upper surface of the insulating layer and the first conductor, forming a material layer over the flattened upper surface of the insulating layer and the first conductor and flattening an upper portion of the material layer while leaving intact a lower portion of the material layer over the insulating layer and the first conductor.

System having improved surface planarity for bit material deposition

Several methods of removing contaminant particles from a surface of a substrate are disclosed herein. In one embodiment, the method includes directing an incompressible fluid spray onto a surface of a substrate to remove contaminant particles from the surface. In an embodiment, the surface of the substrate and the nozzle are both immersed in an incompressible fluid. The fluid can flow across the surface of the substrate to remove the contaminant particles from the area. The fluid spray can be positioned normal to the substrate surface, or can be positioned at an angle relative to the substrate surface.

Wafer cleaning with immersed stream or spray nozzle

An improved composition and method for cleaning the surface of a semiconductor wafer are provided. The composition can be used to selectively remove a low-k dielectric material such as silicon dioxide, a photoresist layer overlying a low-k dielectric layer, or both layers from the surface of a wafer. The composition is formulated according to the invention to provide a desired removal rate of the low-k dielectric and/or photoresist from the surface of the wafer. By varying the fluorine ion component, and the amounts of the fluorine ion component and acid, component, and controlling the pH, a composition can be formulated in order to achieve a desired low-k dielectric removal rate that ranges from slow and controlled at about 50 to about 1000 angstroms per minute, to a relatively rapid removal of low-k dielectric material at greater than about 1000 angstroms per minute. The composition can also be formulated to selectively remove a photoresist layer, leaving the underlying low-k dielectric layer essentially intact.

Compositions for dissolution of low-k dielectric films, and methods of use

Container structures for use in integrated circuits and methods of their manufacture without the use of mechanical planarization such as chemical-mechanical planarization (CMP), thus eliminating CMP-induced defects and variations. The methods utilize localized masking of holes for protection of the inside of the holes during non-mechanical removal of exposed surface layers. The localized masking is accomplished through differential exposure of a resist layer to electromagnetic or thermal energy. The container structures are adapted for use in memory cells and apparatus incorporating such memory cells, as well as other integrated circuits.

Localized masking for semiconductor structure development

The invention includes methods of fabricating integrated circuitry and semiconductor processing polymer residue removing solutions. In one implementation, a method of fabricating integrated circuitry includes forming a conductive metal line over a semiconductor substrate. The conductive line is exposed to a solution comprising an inorganic acid, hydrogen peroxide and a carboxylic acid buffering agent. In one implementation, a method of fabricating integrated circuitry includes forming an insulating layer over a semiconductor substrate. A contact opening is at least partially formed into the insulating layer. The contact opening is exposed to a solution comprising an inorganic acid, hydrogen peroxide and a carboxylic acid buffering agent. In one implementation, a semiconductor processing polymer residue removing solution comprises an inorganic acid, hydrogen peroxide and a carboxylic acid buffering agent. Other aspects and implementations are contemplated.

Methods of fabricating integrated circuitry

Methods for forming the lower electrode of a capacitor in a semiconductor circuit, and the capacitors formed by such methods are provided. The lower electrode is fabricated by forming a texturizing underlayer and then depositing a conductive material thereover. In one embodiment of a method of forming the lower electrode, the texturizing layer is formed by depositing a polymeric material comprising a hydrocarbon block and a silicon-containing block, over the insulative layer of a container, and then subsequently converting the polymeric film to relief or porous nanostructures by exposure to UV radiation and ozone, resulting in a textured porous or relief silicon oxycarbide film. A conductive material is then deposited over the texturizing layer resulting in a lower electrode have an upper roughened surface. In another embodiment of a method of forming the lower electrode, the texturizing underlayer is formed by depositing overlying first and second conductive metal layers and annealing the metal layers to form surface dislocations, preferably structured as a periodic network. A conductive metal is then deposited in gaseous phase, and agglomerates onto the surface dislocations of the texturizing layer, forming nanostructures in the form of island clusters. The capacitor is completed by depositing a dielectric layer over the formed lower electrode, and forming an upper capacitor electrode over the dielectric layer. The capacitors are particularly useful in fabricating DRAM cells.

Method for enhancing electrode surface area in DRAM cell capacitors

A composition and methods for using the composition in removing processing byproducts is provided. The composition can be non-aqueous or semi-aqueous. The non-aqueous composition includes a non-aqueous solvent and one or more components including a fluoride compound and a pyridine compound. The semi-aqueous composition includes glacial acetic acid and one or more components including a fluoride compound and a pyridine compound. The composition can be used in removing processing byproducts from substrate assembly, including MRAM devices, that include at least a metal containing region and processing byproducts, where removing the processing byproducts includes exposing the substrate assembly to the composition for a time effective to remove at least a portion of the processing byproducts.

Compositions for removal of processing byproducts and method for using same

A method for forming an MRAM bit is described that includes providing a covering layer over an integrated circuit structure. In one embodiment, the covering layer includes tantalum. A first mask layer is formed over the covering layer followed by a second mask layer. The first mask layer and second mask layer are etchable by the same etching process. The first and second mask layer are etched. Etch residue is removed from the first and second mask layers. The first mask layer is then selectively removed and the second mask layer remains.

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Boise, ID, United States of America

Donald L Yates