Advanced Micro Devices Corporation

American Microsystems, Inc.

Donald L Wollesen

Yowjuang William Liu

Sunil Narayan Shabde

Matthew S Buynoski

Yu Nan Sun

Ming-Ren Lin

Richard C Blish

Nguyen Duc Bui

Peng Fang

Homi Fatemi

Deepak K Nayak

Jacob D Haskell

Glen P Gilfeather

Craig S Sander

Carl Robert Huster

Concetta E Riccobene

Bryan M Tracy

John T Yue

Philip S Shiota

Richard P Rouse

William P Meuli

Huynh P Tan

A device structure and method for a non-volatile semiconductor device comprises a trenched floating gate and a control gate and further includes a source region, a drain region, a channel region, and an inter-gate dielectric layer. The trenched floating gate is formed in a trench etched into the semiconductor substrate. The trenched floating gate has a top surface which is substantially planar with a top surface of the substrate. The source and drain region have a depth approximately equal to or greater than the depth of the trench and partially extend laterally underneath the bottom of the trench. The inter-gate dielectric layer is formed on the top surface of the trenched floating gate, and the control gate is formed on the inter-gate dielectric layer. In one embodiment, the device structure also includes sidewall dopings that are implanted regions formed in the semiconductor substrate which extend substantially vertically along the length of the trench. The sidewall dopings are immediately contiguous the vertical sides of the trench and laterally separate the trench from the source region and the drain region.

Trenched gate non-volatile semiconductor method with the source/drain regions spaced from the trench by sidewall dopings

A Metal Oxide Semiconductor (MOS) transistor and method for improving device scaling comprises a trenched polysilicon gate formed within a trench etched in a semiconductor substrate and further includes a source region a drain region and a channel region. The source and drain region are laterally separated by the trench in which the trenched polysilicon gate is formed and partially extend laterally beneath the bottom surface of the trench. The channel region is formed in the silicon substrate beneath the bottom surface of the trench. In one embodiment the top surface of the trenched polysilicon gate is substantially planar to the substrate surface. In another embodiment the top surface and a portion of the trenched polysilicon gate are disposed above the substrate surface.

Trenched gate metal oxide semiconductor device and method

A method is provided for obtaining an accurate image of a two-dimensional junction profile of a semiconductor device. Embodiments include sectioning a sample to be analyzed through the active transistor, either at a 90&deg; angle to the planar surface or at a desired angle, as by a focused ion beam (FIB) apparatus. The sectioned transistor can be analyzed directly on the exposed silicon, or the exposed silicon of the cross-section can be passivated with a thin film material such as silicon dioxide, or with an undoped semiconductor material such as silicon or germanium. The electrodes (i.e., source, gate, drain and substrate electrodes) of the sample active transistor are then connected so they can be individually electrically biased. The prepared sample is placed in a conventional voltage contrast SEM, and the electrodes are selectively biased to produce a voltage contrast while being imaged by the voltage contrast SEM, thereby resulting in detailed SEM images of the active regions and depletion spreads.

Method for profiling semiconductor device junctions using a voltage contrast scanning electron microscope

A silicon oxide insulator (SOI) device includes an SOI layer supported on a silicon substrate. A body region is disposed on the SOI layer, and the body region is characterized by a first conductivity type. Source and drain regions are juxtaposed with the body region, with the source and drain regions being characterized by a second conductivity type. A transition region is disposed near the body region above the SOI layer, and the conductivity type of the transition region is established to be the first conductivity type for suppressing floating body effects in the body region and the second conductivity type for isolating the body region. An ohmic connector contacts the transition region and is connected to a drain power supply when the source and drain are doped with N-type dopants. On the other hand, the power supply is a source power supply when the source and drain are doped with P-type dopants. SOI bipolar transistors, pinch resistors, and diodes, all incorporating transition regions, are also disclosed.

Silicon oxide insulator (SOI) semiconductor having selectively linked body

A programmable anti-fuse is formed simultaneously with transistors and other devices on a semiconductor substrate. Embodiments include an anti-fuse comprising a doped active region in the substrate, such as an n&plus; region, a gate oxide layer, and a gate, such as polysilicon, of a minimum size according to design rules. The anti-fuse is programmed by passing a current through it sufficient to cause its gate oxide layer to fail. The inventive anti-fuse is formed by simply altering the patterning of layers that need to be formed for other devices on the substrate. Therefore, it is formed without added manufacturing costs.

Thin oxide anti-fuse

A silicon on insulator (SOI) device includes an electrically-conducting interface region along a portion of the interface between the insulator and a semiconductor layer atop the insulator. The electrically-conducting interface region provides a &ldquo;leaky&rdquo; electrical coupling between the body and source regions of a transistor device such as a &ldquo;MOSFET&rdquo;, thereby reducing floating body effects of the device. A method of forming such a semiconductor device includes forming the electrically-conducting interface region by damaging or implanting materials in the insulator and/or the semiconductor in the vicinity of the interface therebetween. The method may include producing a stepped interface region, such as by etching, in order to aid properly locating the transistor device relative to the electrically-conducting interface region.

Leaky lower interface for reduction of floating body effect in SOI devices

A method is provided for obtaining an accurate image of a two-dimensional junction profile of a semiconductor device. Embodiments include sectioning a sample to be analyzed through the active transistor, either at a 90&deg; angle to the planar surface or at a desired angle, as by a focused ion beam (FIB) apparatus. The sectioned transistor can be analyzed directly on the exposed silicon, or the exposed silicon of the cross-section can be passivated with a thin film material such as silicon dioxide, or with an undoped semiconductor material such as silicon or germanium. The electrodes (i.e., source, gate, drain and substrate electrodes) of the sample active transistor are then connected so they can be individually electrically biased. A direct current (DC) potential is imposed on an active region of the prepared sample, and a small alternating current (AC) potential is imposed on the DC potential. The active region is then scanned using a conventional atomic force micrograph (AFM) or scanning capacitance micrograph (SCM) tip as an AC signal detector to generate an accurate image of the active region.

Junction profiling using a scanning voltage micrograph

Method for determining the robustness of a device to soft errors generated by alpha-particle and/or cosmic ray strikes. In one embodiment, the method includes the steps of estimating energies of the alpha-particle and/or cosmic ray strikes; computing a number of electron-hole pairs generated for a predetermined distance of travel by the alpha-particle and/or cosmic ray into the device based on the estimated energies; computing the absorption coefficient in silicon for a light pulse with a predetermined wavelength; computing a first pulse width/intensity for the light pulse to generate the number of electron-hole pairs for the predetermined distance of travel by the light pulse into the device; producing the light pulse, the light pulse having a light pulse energy which is controlled by a pulse width and an intensity, wherein the pulse width/intensity is at a second pulse width/intensity which is less than the first pulse width/intensity and the light pulse energy is at a first light pulse energy which is low enough to avoid generating soft errors in the device; applying the light pulse to the device at a predetermined location; varying the light pulse energy to a second light pulse energy to generate a soft error; and detecting soft errors in the device. The present invention additionally provides an inexpensive method that would accurately simulate an alpha-particle and/or cosmic ray strike in predetermined areas of a memory cell.

Method and apparatus for determining the robustness of memory cells to alpha-particle/cosmic ray induced soft errors

Complementary metal-oxide-semiconductor (CMOS) transistors (,) are formed with vertical channel regions (,) on an insulator substrate (,). Highly doped polysilicon gates (,) are formed in trenches (,) to extend laterally around the channel regions (,) as insulatively displaced therefrom by gate insulators (,) that are grown on the sidewalls of the trenches (,). The transistors (,), which are formed in respective mesas (,) have deeply implanted source regions (,) that are ohmically connected to the semiconductor surface via respective source connector regions (,).

Method for fabricating a trench-gated vertical CMOS device

A device structure and method for a non-volatile semiconductor device comprises a trenched floating gate and a control gate and further includes a source region, a drain region, a channel region, and an inter-gate dielectric layer. The trenched floating gate is formed in a trench etched into the semiconductor substrate. The trenched floating gate has a top surface which is substantially planar with a top surface of the substrate. The source and drain have a depth approximately equal to or greater than the depth of the trench and partially extend laterally underneath the bottom of the trench. The inter-gate dielectric layer is formed on the top surface of the trenched floating gate, and the control gate is formed on the inter-gate dielectric layer. In one embodiment, the device structure also includes sidewall dopings that are implanted regions formed in the semiconductor substrate which extend substantially vertically along the length of the trench. The sidewall dopings are immediately contiguous the vertical sides of the trench and laterally separate the trench from the source region and the drain region.

Trenched gate non-volatile semiconductor device with the source/drain regions spaced from the trench by sidewall dopings

A method and apparatus for controlling the growth of an oxide, such as a gate oxide, in a semiconductor device manufacturing process takes into consideration the ambient atmospheric pressure in order to reduce the variance in gate oxide thicknesses between wafer lots. The pressure in the oxide diffusion tube is maintained at a constant pressure near the ambient atmospheric pressure during the oxide diffusion process. Alternatively, the furnace time is changed from lot to lot as a function of changes in the ambient atmospheric pressure in order to maintain the gate oxide thickness at a constant value between wafer lots.

Method and apparatus for controlling the thickness of a gate oxide in a semiconductor manufacturing process

A method for manufacturing a field effect transistor (,) includes steps of forming a gate stack (,) on the surface (,) of a semiconductor substrate (,), and defining source/drain regions (,) on either side of the gate stack and a channel region (,) under the gate stack. The channel region has one end (,) proximate a first source/drain region and another end (,) proximate a second source/drain region. The method further includes forming a masking layer (,) on the surface of the semiconductor substrate. The masking layer has a nominal alignment position and a misalignment tolerance. The method still further includes implanting doping ions in the semiconductor substrate to asymmetrically dope the field effect transistor, including selecting a tilt angle and a rotation angle (B, D, F, H) sufficient to ensure shadowing of one end of the channel region from implantation of the doping ions.

Method for manufacturing asymmetric channel transistor

A fully recessed device structure and method for low power applications comprises a trenched floating gate, a trenched control gate and a single wrap around buried drain region. The trenched floating gate and the trenched control gate are formed in a single trench etched into a well junction region in a semiconductor substrate to provide a substantially planar topography. The fully recessed structure further comprises a buried source region, and a buried drain region that are each formed in the well junction region laterally separated by the trench. The upper boundaries of the buried source region and the buried drain region are of approximately the same depth as the top surface of the trenched floating gate. In one embodiment of the present invention the buried drain region has a lower boundary which partially extends laterally underneath the bottom surface of the trench to form a drain junction disposed along portions of the sidewall and bottom of the trench, and the buried source region has a lower boundary which is approximately less than the depth of the trench. In another embodiment of the present invention the buried source region has a lower boundary which partially extends laterally underneath the bottom surface of the trench to form a source junction disposed along portions of the sidewall and bottom of the trench, and the buried drain region has a lower boundary which is approximately less than the depth of the trench. In one embodiment of the present invention, sidewall dopings are formed in the substrate to shield the trenched control gate from the buried source and buried drain regions.

Growing community of inventors

Saratoga, CA, United States of America

Donald L Wollesen