International Business Machines Corporation

Other

Globalfoundries Inc.

Donald J Samuels

Allen H Gabor

Jack Allan Mandelman

Gary Bela Bronner

Shahid Ahmad Butt

Roger J Yerdon

William H Advocate

Maharaj Mukherjee

Matthew Earl Colburn

Mark Alan Lavin

Jeanne P Bickford

Matthew R Wordeman

Howard Smith Landis

Scott David Halle

Heinz Hoenigschmid

Henning Haffner

Scott Marshall Mansfield

Rama Nand Singh

Edward W Conrad

William C Leipold

Geng Han

Burn J Lin

Orest Bula

Scott Josef Bukofsky

Alan C Thomas

Daniel C Cole

Zachary Baum

Ramya Viswanathan

Christopher Adam Feild

Dominique L Nguyen-Ngoc

Allan O Cruz

Michelle Gill

David V MacDonnell, Ii

A method of mask correction where two independent process models are analyzed and co-optimized simultaneously. In the method, a first lithographic process model simulation is run on a computer system that results in generating a first mask size in a first process window. Simultaneously, a second hard mask open etch process model simulation is run resulting in generating a second mask size in a second process window. Each first lithographic process model and second hard mask open etch process model simulations are analyzed in a single iterative loop and a common process window (PW) optimized between lithography and etch is obtained such that said first mask size and second mask size are centered between said common PW. Further, an etch model form is generated that accounts for differences in an etched pattern due to variation in three-dimensional photoresist profile, the model form including both optical and density terms that directly relate to an optical image.

Method of simultaneous lithography and etch correction flow

Techniques, systems, and methods are provided for optimizing pattern density fill patterns for integrated circuits. The method includes adjusting an area of a scribe line and a density of dummy fill shapes in the adjusted scribe line, while maintaining an area of the die, to achieve a pattern density associated with technology ground rules for a particular design of the die.

Methods and systems to meet technology pattern density requirements of semiconductor fabrication processes

Methods of forming line ends and a related memory cell including the line ends are disclosed. In one embodiment, the method includes forming a first device element and a second device element separated from the first device element by a space; and forming a first line extending from the first device element, the first line including a bulbous line end over the space and distanced from the first device element, and a second line extending from the second device element, the second line including a bulbous line end over the space and distanced from the second device element.

Line ends forming

Methods of forming adjacent polyconductor line ends and a mask therefor are disclosed. In one embodiment, the method includes forming a polyconductor layer over an isolation region; forming a mask over the polyconductor layer, the mask including shapes to create the polyconductor line ends and a correction element to ensure a designed proximity of the polyconductor line ends; and etching the polyconductor layer using the patterned photoresist mask to create the adjacent polyconductor line ends, wherein the correction element is removed during the etching.

Polyconductor line end formation and related mask

A method, system and program product for comparing a junk fax image stored in a database to an incoming facsimile image to determine whether the incoming facsimile image is a junk fax. If the facsimile image is a junk fax, the image is either deleted or the communication terminated. The invention also provides a junk fax determinator by which an incoming facsimile image can be designated as a junk fax. In one embodiment, a recipient (user) can make the determination as to whether the incoming facsimile image is a junk fax and generate a personal junk fax database. In another embodiment, the recipient (user) can scan a hard copy document to form an incoming facsimile image, which can be saved as a junk fax in a personal junk fax database.

Facsimile system, method and program product with junk fax disposal

A method of designing lithographic masks is provided where mask segments used in a model-based optical proximity correction (MBOPC) scheme are adaptively refined based on local image information, such as image intensity, gradient and curvature. The values of intensity, gradient and curvature are evaluated locally at predetermined evaluation points associated with each segment. An estimate of the image intensity between the local evaluation points is preferably obtained by curve fitting based only on values at the evaluation points. The decision to refine a segment is based on the deviation of the simulated image threshold contour from the target image threshold contour. The output mask layout will provide an image having improved fit to the target image, without a significant increase in computation cost.

Method for adaptive segment refinement in optical proximity correction

A first aspect of the present invention is a method of determining an optical proximity correction for a primary feature having sub-resolution assist features for increasing the depth of focus of the primary features, comprising: generating a line/space pair; placing sub-resolution assist features on opposite sides of the line of the line/space pair; generating a set of linewidth biases; applying the set of linewidth biases to the line of the line/space pair to generate a set of biased-line/space pairs; determining for each biased-line/space pair, a deviation from a design linewidth of the line/space pair when the set of biased-line/space pairs are printed or simulated; and determining from the deviation a correction bias to apply to the line of the line/space pair. The invention also encompasses apparatus and computer programs for carrying out the methods.

Method of optical proximity correction with sub-resolution assists

A computer operated process ( ) for inspecting patterns ( ) on an object ( ) includes establishing different mismatch margins for different patterns ( ). A strict margin is associated with the pattern ( ) in a critical area ( ), and a relaxed margin is associated with the pattern ( ) in a non-critical area ( ). The inspection process ( ) rejects the object ( ) as being defective if a mismatch between a pattern ( ) and its respective master pattern ( ) exceeds a corresponding mismatch margin. Therefore, the inspection process ( ) maintains a high standard for the pattern ( ) in the critical area ( ) and eases the standard for the pattern ( ) in the non-critical area ( ).

Process for inspecting an object

Image shortening in a photolithographic process is substantially reduced by using sub-resolution reticle features to alter the aerial image in the shortened regions. The use of such sub-resolution reticle features is simple to implement in a design system, and allows for increased feature aspect ratio as well as overlap to other critical features.

Method to overcome image shortening by use of sub-resolution reticle features

A method, and a system for employing the method, for providing a modified optical proximity correction (OPC) for correcting distortions of pattern lines on a semiconductor circuit wafer. The method comprises producing a mask having one or more pattern regions, and producing the semiconductor circuit wafer from the mask. The pattern regions include one or more non-edge pattern regions located adjacent to other of the non-edge pattern regions on the mask. The pattern regions further include one or more edge pattern regions located at or near an area on the mask not having the other non-edge pattern regions. The edge pattern regions have widths calculated to minimize the variance in dimensions between one or more pattern lines on the semiconductor circuit wafer formed from them and one or more pattern lines on the semiconductor circuit wafer formed from the non-edge pattern regions. The distances between any two of the pattern regions are calculated to minimize the variance in dimensions between the one or more pattern lines formed from the edge pattern regions and the one or more pattern lines formed from the non-edge pattern regions. The above producing step includes producing the semiconductor circuit wafer from the mask having the pattern lines formed from the non-edge pattern regions and having the pattern lines formed from the edge pattern regions, where the pattern lines formed from the non-edge regions are permitted to differ in distances between them.

Dummy feature reduction using optical proximity effect correction

The present invention provides a method and an optical lithographic system which eliminates the standing wave effect typically observed in photoresists without the need for altering the thickness of the photoresist, utilizing an anti-reflective coating material, or changing the light source. Specifically, the present invention compensates for standing waves by exposing the photoresist with light from a light source at different phases. That is, in the present invention there is a change in light exposure from a single dose at one phase to a plurality of doses at different phases; therefore dispersing the effects of the standing wave at each of those phases which in turn eliminates the standing wave.

Elimination of standing waves in photoresist

A method is presented here that enables one to improve the prediction for the printed structures of circuit patterns in a microchip, thereby potentially aiding in the design of the microchip circuitry. This method comprises the steps of determining, by applying process bias and corner curvature rules to a real mask image, a simulated structure for the mask used in optical projection lithography; and determining, by applying optical and process proximity correction rules to said simulated mask structure, a more accurate prediction for the structures printed on the wafer. Preferably the simulated mask structure is determined by applying a symmetric bias consistent with a mask build process to the real mask image, adjusting predetermined features of the real mask image such as corners or narrow lines, and applying a reverse symmetric bias to the adjusted real mask image.

Method of modifying a microchip layout data set to generate a predicted mask printed data set

Disclosed herein is an arrangement of memory cells in which the spacing between back-to-back trench capacitors is defined at less than 1 F spacing. A pure phase edge mask is used to define such trench patterns having less than 1 F spacing. The reduction in the trench-to-trench spacing results in increased separation between the trench and the near edge of the gate conductor. This increase in the trench to gate conductor spacing, in turn, permits the channel doping concentration to be decreased, with a corresponding increase in ON current to be realized. In alternative embodiments, a pure phase edge mask or a blocked phase edge mask can be used to define trench patterns in which the width of trenches is increased to form storage capacitors having higher capacitance. In such embodiments, the spacing between back-to-back trenches can be reduced, such that the total separation between the outer edges of adjacent trenches is maintained at about 3 F or less.

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Silverthorne, CO, United States of America

Donald J Samuels