Nvidia Corporation

Don Templeton

Sunil Rao Sudhakaran

Zuhair Bokharey

Brian Schieck

Yaping Zhou

Jayprakash Chipalkatti

Prashant Pathak

Wenjun Shi

Jim Dobbins

Julie Lam

Sheetal Jain

Narayan Kulshrestha

Luke Y Chang

An IC package including an integrated circuit die having a major surface and one or more solder bumps located on the major surface in at least one corner region of the major surface and a substrate having a surface, the surface including bump pads thereon. The major surface of the integrated circuit die faces the substrate surface, the one or more solder bumps are bonded to individual ones of the bump pads to thereby form a bond joint, the major surface of the integrated circuit die has a footprint area of at least about 400 mm. A ratio of a coefficient of thermal expansion of the substrate (CTE) to a coefficient of thermal expansion of the integrated circuit die (CTE) is at least about 3:1. A method of manufacturing an IC package is also disclosed.

IC package design and methodology to compensate for die-substrate CTE mismatch at reflow temperatures

A die package is disclosed through which power domains within the chip may be isolated by removing vias within the package substrate, rather than power gating. Multiple substrate options may be configured without specific vias. This eliminates the need to design power gating circuitry into the die, freeing up that die area for more functional logic. The solution allows the die package to retain the same pinout for use by PCB designers, regardless of which power domains are gated.

Package level power gating

Systems and methods that facilitate resistance and capacitance balancing are presented. In one embodiment, a system comprises: a plurality of ground lines configured to ground components; and a plurality of signal bus lines interleaved with the plurality of ground lines, wherein the interleaving is configured so that plurality of signal bus lines and plurality of ground lines are substantially evenly spaced and the plurality of signal bus lines convey a respective plurality of signals have similar resistance and capacitance constants that are balanced. The plurality of signals can see a substantially equal amount ground surface and have similar amounts of capacitance. The plurality of signal bus lines can have similar cross sections and lengths with similar resistances. The plurality of signal bus lines interleaved with the plurality of ground lines can be included in a two copper layer interposer design with one redistribution layer (RDL).

Resistance and capacitance balancing systems and methods

In one embodiment, a system comprises: a plurality of aggressor bus lines; and a plurality of differential pair bus lines that are located in relatively parallel close proximity to the plurality of aggressor bus lines, wherein at least two of the plurality of differential pair bus lines change location with respect to each other at a point that has a cancelling affect on cross talk from the plurality of aggressor bus lines, wherein the change includes cross over routing. The plurality of differential pair bus lines can convey differential clock signals. The routing of the plurality of differential pair bus lines is substantially parallel to one another before and after the change.

Cross talk reduction differential cross over routing systems and methods

Growing community of inventors

Santa Clara, CA, United States of America

Don Templeton