Nxp B.v.

Ipdia

Murata Manufacturing Co., Ltd.

Dominique Yon

Patrice Gamand

Francois Neuilly

David D R Chevrie

Lucie A Rousseville

Sebastien Jacqueline

Sophie Gaborieau

The present invention relates to a method and system for testing integrity of a passivation layer () covering a semiconductor device. A structured layer of electrically conducting material () is deposited onto at least a portion of a top surface of a substrate () of the semiconductor device. The structured layer () comprises a plurality of bands () connected to at least two contacts () and disposed on the at least a portion of the top surface such that one of consecutive bands () and consecutive portions of the bands () are connected to different contacts (). A passivation layer () is deposited onto the at least a portion of the top surface of the substrate () and the structured layer () such that material of the passivation layer() is disposed between the bands of conducting material () and on top of the structured layer (). Electrically conducting material is then deposited onto the passivation layer () and a resistance is measured between the at least two contacts (). An indication with respect to integrity of the passivation layer () is determined in dependence upon the measured resistance.

Embedded structure for passivation integrity testing

The present invention provides a method for making a vertical interconnect through a substrate. The method makes use of a sacrificial buried layerarranged in between the first sideand the second sideof a substrate. After having etched trenchesand' from the first side, the sacrificial buried layerfunctions as a stop layer during etching of holesand&#x2032; from the second side, therewith protecting the trenches from damage during overetch of the holes. The etching of trenches is completely decoupled from etching of the holes providing several advantages for process choice and device manufacture. After removing part of the sacrificial buried layer to interconnect the trenches and the holes, the resulting vertical interconnect hole is filled to form a vertical interconnect.

Electronic device and method for making the same

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Saint Aubin sur Mer, France

Dominique Yon